Integer Arithmetic Research Articles

Integration of SMT-solvers in B and Event-B development environments

Software development in B and Event-B generates proof obligations that have to be discharged using theorem provers. The cost of such developments depends directly on the degree of automation and efficiency of theorem proving techniques for the logics in which these lemmas are expressed. This paper presents and formalizes an approach to transform a class of proof obligations essentially similar to those generated in the Rodin platform into the input language of a category of automatic theorem provers known as SMT-solvers. The work presented in the paper handles proof obligations with Booleans, integer arithmetics, basic sets and relations and has been implemented as a plug-in for Rodin.

Outer billiards on the Penrose kite: Compactification and renormalization

We give a fairly complete analysis of outer billiards on the Penrose kite. Our analysis reveals that this $2$-dimensional dynamical system has a $3$-dimensional compactification, a certain polyhedron exchange map defined on the $3$-torus, and that this $3$-dimensional system admits a renormalization scheme. The two features allow us to make sharp statements concerning the distribution, large- and fine-scale geometry, and hidden algebraic symmetry, of the orbits. One concrete result is that the union of the unbounded orbits has Hausdorff dimension $1$. We establish many of the results with computer-aided proofs that involve only integer arithmetic.

Min-Sum Algorithm for LDPC Codes Based on Integer Operation

Low-Density Parity-Check (LDPC) codes are widely interested by the scholars researching on the channel coding for its near Shannon limit performance and relatively simple decoding structure. In this paper, LDPC min-sum decoding algorithm is in-depth studied, and the specific methods of the maximum average mutual information quantization are analyzed and deduced. With this method to quantify the initial message, each iteration of the variable messages and check messages becomes integer, then the min-sum decoding algorithm based on integer arithmetic is implemented. Simulation results show that the performance of 7-bit maximum average mutual information quantization under the min-sum algorithm is very close to the performance of precision floating point operation based on sum-product decoding algorithm. At the same time all the variables in the algorithm with fixed-length integer, and the decoding time is greatly reduced. So it is easy for hardware implementation.

Cubic Root Extractors of Gaussian Integers and Their Application in Fast Encryption for Time-Constrained Secure Communication

There are settings where encryption must be performed by a sender under a time constraint. This paper de-scribes an encryption/decryption algorithm based on modular arithmetic of complex integers called Gaus-sians. It is shown how cubic extractors operate and how to find all cubic roots of the Gaussian. All validations (proofs) are provided in the Appendix. Detailed numeric illustrations explain how to use the method of digital isotopes to avoid ambiguity in recovery of the original plaintext by the receiver.

A FPGA system for QRS complex detection based on Integer Wavelet Transform

Due to complexity of their mathematical computation, many QRS detectors are implemented in software and cannot operate in real time. The paper presents a real-time hardware based solution for this task. To filter ECG signal and to extract QRS complex it employs the Integer Wavelet Transform. The system includes several components and is incorporated in a single FPGA chip what makes it suitable for direct embedding in medical instruments or wearable health care devices. It has sufficient accuracy (about 95%), showing remarkable noise immunity and low cost. Additionally, each system component is composed of several identical blocks/cells what makes the design highly generic. The capacity of today existing FPGAs allows even dozens of detectors to be placed in a single chip. After the theoretical introduction of wavelets and the review of their application in QRS detection, it will be shown how some basic wavelets can be optimized for easy hardware implementation. For this purpose the migration to the integer arithmetic and additional simplifications in calculations has to be done. Further, the system architecture will be presented with the demonstrations in both, software simulation and real testing. At the end, the working performances and preliminary results will be outlined and discussed. The same principle can be applied with other signals where the hardware implementation of wavelet transform can be of benefit.

Three dimensional extension of Bresenham’s Algorithm with Voronoi diagram

Bresenham’s Algorithm for plotting a two-dimensional line segment is elegant and efficient in its deployment of mid-point comparison and integer arithmetic. It is natural to investigate its three-dimensional extensions. In so doing, this paper uncovers the reason for little prior work. The concept of the mid-point in a unit interval generalizes to that of nearest neighbours involving a Voronoi diagram. Algorithmically, there are challenges. While a unit interval in two-dimension becomes a unit square in three-dimension, “squaring” the number of choices in Bresenham’s Algorithm is shown to have difficulties. In this paper, the three-dimensional extension is based on the main idea of Bresenham’s Algorithm of minimum distance between the line and the grid points. The structure of the Voronoi diagram is presented for grid points to which the line may be approximated. The deployment of integer arithmetic and symmetry for the three-dimensional extension of the algorithm to raise the computation efficiency are also investigated.

Fast sort of floating-point data for data engineering

In this paper, a novel external sort algorithm that improves the speedup of the sorting of floating-point numbers has been described. Our algorithm decreases the computation time significantly by applying integer arithmetic on floating-point data in the IEEE-754 standard or similar formats. We conducted experiments with synthetic data on a 32-processor Linux cluster; in the case of the internal sort alone, the Giga-byte sorting achieved approximately fivefold speedups. Furthermore, the sorting achieved twofold or greater improvements over the typical parallel sort method, network of workstations (NOW)-sort. Moreover, the sorting scheme performance is independent of the computing platform. Thus, our sorting method can be successfully applied to binary search, data mining, numerical simulations, and graphics.

An iterative logarithmic multiplier

Digital signal processing algorithms often rely heavily on a large number of multiplications, which is both time and power consuming. However, there are many practical solutions to simplify multiplication, like truncated and logarithmic multipliers. These methods consume less time and power but introduce errors. Nevertheless, they can be used in situations where a shorter time delay is more important than accuracy. In digital signal processing, these conditions are often met, especially in video compression and tracking, where integer arithmetic gives satisfactory results. This paper presents a simple and efficient multiplier with the possibility to achieve an arbitrary accuracy through an iterative procedure, prior to achieving the exact result. The multiplier is based on the same form of number representation as Mitchell’s algorithm, but it uses different error correction circuits than those proposed by Mitchell. In such a way, the error correction can be done almost in parallel (actually this is achieved through pipelining) with the basic multiplication. The hardware solution involves adders and shifters, so it is not gate and power consuming. The error summary for operands ranging from 8 bits to 16 bits indicates a very low relative error percentage with two iterations only. For the hardware implementation assessment, the proposed multiplier is implemented on the Spartan 3 FPGA chip. For 16-bit operands, the time delay estimation indicates that a multiplier with two iterations can work with a clock cycle more than 150 MHz, and with the maximum relative error being less than 2%.

Catching the Ouroboros: On debugging non-ground answer-set programs

AbstractAn important issue towards a broader acceptance of answer-set programming (ASP) is the deployment of tools which support the programmer during the coding phase. In particular, methods fordebuggingan answer-set program are recognised as a crucial step in this regard. Initial work on debugging in ASP mainly focused on propositional programs, yet practical debuggers need to handle programs with variables as well. In this paper, we discuss a debugging technique that is directly geared towards non-ground programs. Following previous work, we address the central debugging question why some interpretation is not an answer set. The explanations provided by our method are computed by means of a meta-programming technique, using a uniform encoding of a debugging request in terms of ASP itself. Our method also permits programs containing comparison predicates and integer arithmetics, thus covering a relevant language class commonly supported by all state-of-the-art ASP solvers.

Printing floating-point numbers quickly and accurately with integers

We present algorithms for accurately converting floating-point numbers to decimal representation. They are fast (up to 4 times faster than commonly used algorithms that use high-precision integers) and correct: any printed number will evaluate to the same number, when read again. Our algorithms are fast, because they require only fixed-size integer arithmetic. The sole requirement for the integer type is that it has at least two more bits than the significand of the floating-point number. Hence, for IEEE 754 double-precision numbers (having a 53-bit significand) an integer type with 55 bits is sufficient. Moreover we show how to exploit additional bits to improve the generated output. We present three algorithms with different properties: the first algorithm is the most basic one, and does not take advantage of any extra bits. It simply shows how to perform the binary-to-decimal transformation with the minimal number of bits. Our second algorithm improves on the first one by using the additional bits to produce a shorter (often the shortest) result. Finally we propose a third version that can be used when the shortest output is a requirement. The last algorithm either produces optimal decimal representations (with respect to shortness and rounding) or rejects its input. For IEEE 754 double-precision numbers and 64-bit integers roughly 99.4% of all numbers can be processed efficiently. The remaining 0.6% are rejected and need to be printed by a slower complete algorithm.

Integer SEC-DED codes for low power communications

A new class of SEC-DED codes based on integer arithmetic is presented. The proposed approach is characterized by linear time complexity of coding and decoding procedures and constant time complexity of the single-bit error correction procedure. In addition, the presented codes can protect an arbitrary number of data bits, which makes them suitable for use in a wide range of communication systems.

Hardware/software partitioning and pipelined scheduling on runtime reconfigurable FPGAs

FPGAs are widely used in today's embedded systems design due to their low cost, high performance, and reconfigurability. Partially RunTime-Reconfigurable (PRTR) FPGAs, such as Virtex-2 Pro and Virtex-4 from Xilinx, allow part of the FPGA area to be reconfigured while the remainder continues to operate without interruption, so that HW tasks can be placed and removed dynamically at runtime. We address two problems related to HW task scheduling on PRTR FPGAs: (1) HW/SW partitioning. Given an application in the form of a task graph with known execution times on the HW (FPGA) and SW (CPU), and known area sizes on the FPGA, find an valid allocation of tasks to either HW or SW and a static schedule with the optimization objective of minimizing the total schedule length (makespan). (2) Pipelined scheduling. Given an input task graph, construct a pipelined schedule on a PRTR FPGA with the goal of maximizing system throughput while meeting a given end-to-end deadline. Both problems are NP-hard. Satisfiability Modulo Theories (SMT) is an extension to SAT by adding the ability to handle arithmetic and other decidable theories. We use the SMT solver Yices with Linear Integer Arithmetic (LIA) theory as the optimization engine for solving the two scheduling problems. In addition, we present an efficient heuristic algorithm based on kernel recognition for the pipelined scheduling problem, a technique borrowed from SW pipelining, to overcome the scalability problem of the SMT-based optimal solution technique.

Signed Integer Arithmetic on Spiking Neural P System

Spiking neural P systems are a new computing model incorporating the ideas of spiking neurons into membrane computing. It has been shown that they have powerful computational capability and potential capability in solving computationally hard problems. The paper describes the implementation of signed integer arithmetic operations on spiking neural P system with the inputs and outputs encoded as appropriate sequences of spikes. The present work may be considered as the basis for more complex applications, maybe for constructing computer chips or for solving general mathematical problems.

Matched DDWT ROI Compression Engine for the Imaging Particle Detector

A new multirate DDWT (Double Density Wavelet Transform) matched filter ROI (region of interest) processor for the ICARUS (Imaging Cosmic And Rare Underground Signals) particle detector [Amerio(2004)] has been designed. The ROI extraction engine is based on matched and unmatched Wiener filtering using coupled DWT and DDWT processing. High through-put image-like ICARUS detector data (160MBps data rate per crate) is able to be compressed 600 times using multi-stage compression with ROI extraction. The 32-channel (160MBps data rate) processor has been fully implemented in a low cost FPGA device thanks to Fast Integer Arithmetic Wavelet Transform (FIAWT) [Pólchlopek(2006)] algorithm implementation.

Hardware-Friendly Descreening

Conventional electrophotographic printers tend to produce Moiré artifacts when used for printing images scanned from printed material such as books and magazines. We propose a novel noniterative, nonlinear, and space-variant descreening filter that removes a wide range of Moiré-causing screen frequencies in a scanned document while preserving image sharpness and edge detail. This filter is inspired by Perona-Malik's anisotropic diffusion equation. The amount of diffusion of the image intensity resulting from applying the filter is governed by an edge intensity estimate that is robust under halftone noise. More precisely, the filter extracts a spatial feature vector comprising local intensity gradients estimated from a local window in a presmoothed version of the noisy input image. Tunable nonlinear polynomial functions of this feature vector are then used to perform one iteration of a discrete diffusion controlled by the intensity gradient. The polynomial functions and feature extraction kernels are selected empirically in order to minimize computation while ensuring robust performance across a wide range of test images on a target imaging platform. The algorithm uses integer arithmetic, mostly relying on low-cost bit-wise shift and addition operations, and uses a strictly sequential architecture to provide a cost-effective and robust descreening solution in practical imaging devices including copiers and multifunction printers. We compare the performance of the proposed algorithm to other descreening solutions and demonstrate that the new algorithm improves quality over the existing methods while reducing computation.

Theoretical and empirical convergence results for additive congruential random number generators

Additive Congruential Random Number (ACORN) generators represent an approach to generating uniformly distributed pseudo-random numbers that is straightforward to implement efficiently for arbitrarily large order and modulus; if it is implemented using integer arithmetic, it becomes possible to generate identical sequences on any machine. This paper briefly reviews existing results concerning ACORN generators and relevant theory concerning sequences that are well distributed mod 1 in k dimensions. It then demonstrates some new theoretical results for ACORN generators implemented in integer arithmetic with modulus M = 2 μ showing that they are a family of generators that converge (in a sense that is defined in the paper) to being well distributed mod 1 in k dimensions, as μ = log 2 M tends to infinity. By increasing k , it is possible to increase without limit the number of dimensions in which the resulting sequences approximate to well distributed. The paper concludes by applying the standard TestU01 test suite to ACORN generators for selected values of the modulus (between 2 60 and 2 150), the order (between 4 and 30) and various odd seed values. On the basis of these and earlier results, it is recommended that an order of at least 9 be used together with an odd seed and modulus equal to 2 30 p , for a small integer value of p . While a choice of p = 2 should be adequate for most typical applications, increasing p to 3 or 4 gives a sequence that will consistently pass all the tests in the TestU01 test suite, giving additional confidence in more demanding applications. The results demonstrate that the ACORN generators are a reliable source of uniformly distributed pseudo-random numbers, and that in practice (as suggested by the theoretical convergence results) the quality of the ACORN sequences increases with increasing modulus and order.

Low-dimensional lattice basis reduction revisited

Lattice reduction is a geometric generalization of the problem of computing greatest common divisors. Most of the interesting algorithmic problems related to lattice reduction are NP-hard as the lattice dimension increases. This article deals with the low-dimensional case. We study a greedy lattice basis reduction algorithm for the Euclidean norm, which is arguably the most natural lattice basis reduction algorithm because it is a straightforward generalization of an old two-dimensional algorithm of Lagrange, usually known as Gauss' algorithm, and which is very similar to Euclid's gcd algorithm. Our results are twofold. From a mathematical point of view, we show that up to dimension four, the output of the greedy algorithm is optimal: The output basis reaches all the successive minima of the lattice. However, as soon as the lattice dimension is strictly higher than four, the output basis may be arbitrarily bad as it may not even reach the first minimum. More importantly, from a computational point of view, we show that up to dimension four, the bit-complexity of the greedy algorithm is quadratic without fast integer arithmetic, just like Euclid's gcd algorithm. This was already proved by Semaev up to dimension three using rather technical means, but it was previously unknown whether or not the algorithm was still polynomial in dimension four. We propose two different analyzes: a global approach based on the geometry of the current basis when the length decrease stalls, and a local approach showing directly that a significant length decrease must occur every O (1) consecutive steps. Our analyzes simplify Semaev's analysis in dimensions two and three, and unify the cases of dimensions two to four. Although the global approach is much simpler, we also present the local approach because it gives further information on the behavior of the algorithm.

Eye fixation behaviour in the number bisection task: Evidence for temporal specificity

Together with magnitude representations, knowledge about multiplicativity and parity contributes to numerical problem solving. In the present study, we used eye tracking to document how and when multiplicativity and parity are recruited in the number bisection task. Fourteen healthy adults evaluated whether the central number of a triplet (e.g., 21_24_27) corresponds to the arithmetic integer mean of the interval defined by the two outer numbers. We observed multiplicativity to specifically affect gaze duration on numbers, indicating that the information of multiplicative relatedness is activated at early processing stages. In contrast, parity only affected total reading time, suggesting involvement in later processing stages. We conclude that different representational features of numbers are available and integrated at different processing stages within the same task and outline a processing model for these temporal dynamics of numerical cognition.

An efficient signed digit montgomery multiplication for RSA

In this paper we present an efficient Montgomery multiplier using the signed digit number representation suitable for modular exponentiation, which is the main operation of RSA. The multiplier consists of one level of signed digit adder plus multiplexer through a precomputation. We design the multiplier with the improved signed digit adder using SAMSUNG STD [email protected] 1.8V CMOS Standard Cell Library and compare to multipliers with other previous adders. The proposed modular multiplier can be applied to public key cryptosystems based on integer arithmetic such as RSA, DSA or ECC.

Flat Parametric Counter Automata

In this paper we study the reachability problem for parametric flat counter automata, in relation with the satisfiability problem of three fragments of integer arithmetic. The equivalence between n...