Insulator Wafer Research Articles

A Silicon Nanowire Ferroelectric Field‐Effect Transistor

AbstractThe design and characterization of a Schottky‐type ferroelectric field‐effect transistor based on a nominally undoped silicon nanowire are reported. The nanowire transistor is fabricated by top‐down technology starting from a silicon‐on insulator wafer. A thin ferroelectric Hf0.38Zr0.62O2 layer is integrated via a gate‐first approach. Abrupt Schottky source/drain contacts to the undoped silicon are provided by NiSi2 formation. Two distinct nonvolatile transistor states (programmed and erased) are observed in correspondence to negative and positive polarization in the ferroelectric layer, delivering a memory window of ≈1.5 V and, differently to conventional ferroelectric field effect transistors, yielding an on‐current difference of up to 30%. These results are interpreted as a combination of effects, arising from the proximity of the ferroelectric layer to both the channel and the Schottky‐junction regions. The threshold voltage shift, due to a polarization field acting on the channel, adds up to a polarization field‐driven tuning of the current injection through the Schottky‐source junction. This provides a strategy for manufacturing Schottky‐type nanoscale transistors with the add‐on nonvolatile option, following a complementary metal‐oxide‐semiconductor compatible process. In particular, the device concept is of great interest for achieving nonvolatile polarity modification in reconfigurable field‐effect transistors.

Fabrication of SiNWs-FET Nanostructure Via Atomic Force Microscopy Lithography

The unique electrical properties of silicon nanowires (SiNWs) is one of the reasons it become an attractive transducer for biosensor nowadays. Positive (holes) and negative (electron) charge carriers from SiNWs can simply interact with either positive or negative charge of sensing target. In this paper, we have studied the fabrication of silicon nanowires field effect transistor (SiNWs-FET) nanostructure patterned on 15 Ω resistivity of p-type silicon on insulator (SOI) wafer fabricated via atomic force microscopy lithography technique. To fabricate SiNWs-FET nanostructure, a conductive AFM tip, Cr/Pt cantilever tip, was used then various value of applied voltage, writing speed and relative humidity were studied. Subsequent, followed by wet etching processes, admixture of tetramethylammonium hydroxide (TMAH) and isopropyl alcohol (IPA) were used to remove the undesired of silicon layer and diluted hydrofluoric acid (HF) was used to remove the oxide layer. From the results, it shows that, cantilever tip at 9 V with 0.4 μm/s writing speed and relative humidity between 55% - 60% gives the best formation of silicon oxide to fabricate SiNWs-FET nanostructure.

Study on SOI structure irradiated by electron and annealled treatment using C–V, FTIR and PL

Abstract In this work, the commercial silicon on insulator (SOI) wafers irradiated by 0.5 MeV electrons with a fluence of 1.5⨯1014 ~ 2.3⨯1015 cm−2 and annealed among 150 °C and 300 °C have been studied in detail. The performances of SOI samples are investigated by Geant4, Capacitance - Voltage (C–V), Fourier Transform Infrared Spectroscopy (FTIR) and Photoluminescence (PL). The C–V measurements indicate that capacitance decrease under positive voltage bias with increasing fluence. The free carrier concentration decreases with increasing fluence and increases with rising annealing temperature, which can be attributed to the traps induced by electron irradiation on Si/SiO2 interface. There is only the presence of Si–O bonding from the FTIR absorption peaks exhibiting at ~940, ~960, and ~1170 cm−1. The relative intensity of three peaks become weaker with higher irradiation fluence and annealing under 150 °C, which is in good agreement with the Monte Carlo numerical simulation (Geant4). The PL spectra reveals that there is a strong photoluminescence emission at about 420 nm (2.95 eV), which is ascribed to the radiative recombination centers in SiO2 layer. In addition, weaker peaks of PL emission at 720 nm (1.72 eV) and 835 nm (1.49 eV) are also discussed in this paper.

MEMS-Based Planar Incandescent Microfilaments With Low Voltage Operation

In this article, we report the design and fabrication for planar-type incandescent microfilaments on the silicon on insulator (SOI) wafer. The micro-electro-mechanical systems (MEMS) process with XeF2 etching is used to construct the suspension structure for the reduction of thermal conduction. The fabricated line-type microfilament has a low operation voltage of 4 V. Besides, the operation voltages for the $1\times 4$ , $5\times 5$ , $6\times 6$ , and $7\times 7$ arrays at 50 mtorr are 4.0, 9.0, 9.5, and 9.5 V, respectively. The $1\times 4$ array filament exhibits the measured lifetime of 200 hrs and the predicted lifetime of about 570 hrs. The microfilament has a continuous broadband spectrum that covers from visible light extended to over $3~{\mu }\text{m}$ , which is a suitable light source for near-infrared spectroscopy.

SOI wafer fabricated with extremely thick deposited BOX layer using a surface activated bonding technique at room temperature

The fabrication cost of bonded silicon on insulator (SOI) wafers for customized power devices is high owing to the high temperature required and the very long fabrication process involving both thermal oxidation and bonding. In addition, SOI wafers are contaminated with metallic impurities during the formation of the buried oxide (BOX) layer and the bonding of a silicon layer on the BOX layer. Therefore, we propose an alternative SOI wafer fabrication method combining BOX layer deposition and surface activated bonding at room temperature in a vacuum without any voids. There is also no fixed charge in the deposited BOX layer, and the breakdown voltage of this layer is 11–12 MV cm−1, the same as that for a thermal oxide layer.

Electrostatic arch micro-tweezers

This paper presents a novel electrostatic micro-tweezers to manipulate particles with diameters up to 14 μm. The tweezers consist of two grip-arms mounted to an electrostatically actuated initially curved micro-beam. It exploits bistable equilibria, resulting from a snap-through instability, to close the separation distance between the two arms allowing them to grasp a large range of objects. The tweezers offer further control beyond the snap-through point, via electrostatic actuation, to increase pressure on larger objects or grasp smaller objects. The tweezers are fabricated in a p-type Silicon on Insulator (SOI) wafer. Euler-Bernoulli beam theory is utilized to derive the governing equation of motion taking into account the arms' rotary inertia and the electrostatic fringing field. A reduced-order model (ROM) is developed utilizing two, three and five symmetric modes in a Galerkin expansion. A finite element model (FEM) is also developed to validate the ROM and to study the arm tips' separation as a function of actuation voltage. The five-mode ROM is found to be convergent and accurate except in the vicinity of the snap-through saddle-node bifurcation. Our analysis shows that the tweezers can manipulate micro-particles with diameters ranging from 5 to 12μm with an operating voltage range limited by the snap-back voltage 100.2V and the pull-in voltage 153.2V.

Tunable MEMS VCSEL on Silicon Substrate

We present the design, fabrication, and characterization of a MEMS VCSEL which utilized a silicon on insulator wafer for the microelectromechanical system and encapsulates the MEMS by direct InP wafer bonding in order to improve the protection and control of the tuning element. This can enable more robust fabrication, a larger free spectral range, and bidirectional tuning of the MEMS element. The proposed device uses a high contrast grating mirror on a MEMS stage as the bottom mirror, wafer bondind InP with quantum wells for amplification and a deposited dielectric DBR. A tuning range of 40 nm and a mechanical resonance frequency of $>$ 2 MHz is demonstrated. We present design, fabrication, and characterization of an optically pumped MEMS VCSEL which utilizes a silicon-on-insulator wafer for the microelectromechanical system and encapsulates the MEMS by direct InP wafer bonding, which improves the protection and control of the tuning element. This procedure enables a more robust fabrication, a larger free spectral range, and facilitates bidirectional tuning of the MEMS element. The MEMS VCSEL device uses a high contrast grating mirror on a MEMS stage as the bottom mirror, a wafer-bonded InP with quantum wells for amplification and a deposited dielectric DBR as the top mirror. A 40-nm tuning range and a mechanical resonance frequency in excess of 2 MHz are demonstrated.

Strained Si on Insulator as Potential Material for Forced Stacked Multi-threshold FinFET Based Inverter Considering Ultra Low-Power Applications

This work investigates the performance of strained Si on insulator as potential material for forced stacked multi-threshold FinFET based inverter considering its ultra low-power applications. Using the calibrated exhaustive 3D-TCAD mixed-mode simulation a comparative analysis of conventional and forced stack FinFET based inverters has been performed. The static and dynamic characteristics have been compared with conventional and forced stacked FinFET based inverter. The leakage in standby mode can be reduced through well-defined stack and multi-threshold (VTH) transistors. Channel doping is optimized to get higher VTH devices. To improve the speed of circuits FinFETs are designed on strained Silicon on Insulator (sSOI) wafer. Uniform uniaxial tensile stress in sSOI gives the advantage of high ON current in n-FinFETs. It is observed that using strained FinFETs the maximum delay is reduced below 10 ps and using multi VTH forced stack technique the leakage power is reduced. Hence, forced stack technique based FinFET can evolve as a potential candidate for the future ultra-low power device applications.

A Study of Vacuum Efficiency for Silicon on Insulator Wafers

The development on thinner packages has become the trend and focus in semiconductor packaging industry. The necessity of thinner packages also entails a thinner vertical structure of the integrated circuit (IC) design. As a major contributor on the vertical structure of the IC package, die or wafer is also essential to go thinner. As the wafer goes thinner, various problems may occur during transport and even the back grinding process, itself.
 Wafer warpage is one of the main concerns during the process. The effect of proper vacuuming will play major role in processing SOI wafers. Insufficient vacuum may cause non-planar wafer in contact with the chuck table that may result to poorer grinding and worst broken wafer. 
 Different silicon wafer technology has been released to cater different functionality on different industry markets. One popular silicon technology is Silicon On Insulator (SOI) technology. SOI wafers have a step type passivation wherein the edge of the wafer is observed to have 30um thinner than its center. The stepping effect also contributes to the 0.5mm wafer warpage prior back grinding. Evaluating the effect of vacuum efficiency to eliminate such warpage is discussed on this technical paper.

Mechanical Superheterodyne and Its Use for Low Frequency Vibrations Sensing

Mechanical micro and nano scale devices are being increasingly used for realizing signal processing and logic or computing functions, which until recently were traditionally performed by electronics. Extremely low-power consumption and robustness make mechanical micro structures attractive for implementation in autonomous distributed sensing systems. Heterodyning is one of the most important and indispensable signal processing techniques. In microelectromechanical heterodynes, the frequency mixing is commonly achieved using nonlinear forces, which often limits scalability and the operational range of the device and may lead to undesired dynamic behavior. In this paper, we introduce an approach allowing purely mechanical realization of the superheterodyne principle. The frequency mixing is based on the inertial coupling between two vibratory modes of the device. The architecture is distinguished by linearity of the mixing term with respect to the input inertial and the local oscillator signals. We demonstrate the mixing effect both theoretically and experimentally, using the devices fabricated from a silicon on insulator (SOI) wafer by deep reactive ion etching (DRIE). We show the applicability of the device as a mechanical low frequency vibration sensor. The substrate vibration frequencies down to 25 Hz were measured using a device with a fundamental mode frequency of 4700 Hz.

Geometrical compensation for mode-matching of a (100) silicon ring resonator for a vibratory gyroscope

A geometrical compensation design method in a (100) single crystal silicon (SCS) vibratory ring gyroscope (VRG) has been proposed in order to decrease frequency splits (∆f) caused by anisotropic in-plane Young’s modulus (E) of (100) SCS and realize mode-matching in VRG. The radial width as a function of the E was varied to equalize the effective bending stiffness along the different crystal directions. The finite element analysis (FEA) simulation verified that the ∆f decreased from 260 Hz to 145 Hz after compensation. By optimizing suspending beam dimensions, the simulated ∆f further decreased to 9 Hz. Both uncompensated and compensated resonators of 1-mm diameter were fabricated using a silicon-on insulator (SOI) wafer of a 22-μm-thick device layer. The fabricated devices showed large ∆f because of fabrication error, which is adjusted by electrostatic tuning. After the electrostatic tuning, the measured minimum frequency splits for the compensated and uncompensated VRGs were about 54 Hz and 166 Hz, respectively. The small measured ∆f after the electrostatic tuning indicates that the proposed geometrical compensation is effective in eliminating frequency split caused by anisotropy in elastic constants.

Temperature‐Dependent Noise and Transport in Silicon Two‐Layer Nanowire FETs

Silicon two‐layer (TL) nanowire (NW) field‐effect transistors (FETs) are fabricated by applying a CMOS‐compatible top‐down approach to silicon on insulator (SOI) wafers with additionally epitaxially grown silicon layers. Transport and noise properties of fabricated structures with p‐type conductivity are studied in a wide temperature range (100–300 K). A random telegraph signal (RTS) noise as a special case of trapping‐detrapping processes is registered as a dominant noise component at room temperature. A shift of the characteristic corner (rollover) frequency of the RTS noise to lower frequencies with temperature decreasing is observed. By performing analysis of temperature‐dependent low‐frequency noise, the activation energy and hole capture cross section of a single trap responsible for the RTS noise are estimated to be (0.29 ± 0.02 eV) and (2.22 ± 0.15) ×10−18 cm2, respectively. Obtained values suggest that the trap can be attributed to a vacancy‐boron complex. At the temperature below 200 K fabricated devices demonstrate a clear generation‐recombination noise with power spectral density proportional to 1/f 3/2. Such noise behavior provides the evidence of diffusion‐assisted processes in two‐layer nanowire structures. This confirms the contribution of high‐doped top silicon layer to the transistor transport properties.

Quantum interference in silicon one-dimensional junctionless nanowire field-effect transistors

We investigate the low-temperature transport in 8-nm-diam Si junctionless nanowire field-effect transistors fabricated by top down techniques with a wraparound gate and two different phosphorus doping concentrations. First we extract the intrinsic gate capacitance of the device geometry from a device that demonstrates Coulomb blockade at 12 mK with over 500 Coulomb peaks across a gate-voltage range of 6 V indicating the formation of an island in the entire 150-nm-long nanowire channel. In two other devices, made from silicon on insulator wafers that were doped to an activated dopant concentration of Si:P $4\ifmmode\times\else\texttimes\fi{}{10}^{19}$ and $2\ifmmode\times\else\texttimes\fi{}{10}^{20}\phantom{\rule{4pt}{0ex}}{\text{cm}}^{\ensuremath{-}3}$, we observe quantum interference and use the extracted gate coupling to determine the mean free paths from the dominant energy scale on the gate-voltage axis. For the higher doped device, the analysis yields a mean free path of $4\ifmmode\pm\else\textpm\fi{}2\phantom{\rule{4pt}{0ex}}\text{nm}$, which is on the order of the average spacing of phosphorus atoms and suggests scattering on unactivated or activated dopants. For the device with an implanted phosphorus density of $4\ifmmode\times\else\texttimes\fi{}{10}^{19}\phantom{\rule{4pt}{0ex}}{\text{cm}}^{\ensuremath{-}3}$, the quantum interference effects suggest a mean free path of $10\ifmmode\pm\else\textpm\fi{}2\phantom{\rule{4pt}{0ex}}\text{nm}$, which is comparable to the nanowire width, and thus allows for coherent formation of transversal modes. The results suggest that the low-temperature mobility is limited by scattering on phosphorus dopants rather than the expected surface roughness scattering for nanowires with diameters larger than or comparable to the Fermi wavelength. A temperature-dependent analysis of universal conductance fluctuations indicates a phase-coherence length greater than the nanowire length for temperatures below 1.9 K, and decoherence from one-dimensional electron-electron interactions dominates transport for higher temperatures. Our measurements, therefore, provide insight into scattering and dephasing mechanisms in technologically relevant silicon device geometries, which will help with future design choices with regard to, e.g., doping density.

Germanium vertically light-emitting micro-gears generating orbital angular momentum.

Germanium (Ge) is capturing researchers' interest as a possible optical gain medium implementable on complementary metal-oxide-semiconductor (CMOS) chips. Band-gap engineering techniques, relying mainly on tensile strain, are required to overcome the indirect band-gap nature of bulk Ge and promote electron injection into the direct-gap valley. We used Ge on silicon on insulator (Ge-on-SOI) wafers with a high-crystalline-quality Ge layer to fabricate Ge micro-gears on silicon (Si) pillars. Micro-gears are created by etching a periodic grating-like pattern on the circumference of a conventional micro-disk, resulting in a gear shape. Thermal built-in stresses within the SiO2 layers that encapsulate the micro-gears were used to impose tensile strain on Ge. Biaxial tensile strain values ranging from 0.3-0.5% are estimated based on Raman spectroscopy measurements and finite-element method (FEM) simulations. Multiple sharp-peak resonances within the Ge direct-gap were detected at room temperature by photo-luminescence (PL) measurements. By investigating the micro-gears spectrum using finite-difference time-domain (FDTD) simulations, we identified vertically emitted optical modes with non-zero orbital angular momentum (OAM). To our best knowledge, this is the first demonstration of OAM generation within a Ge light source.

SOI wafer fabricated with a diamond BOX layer using surface activated bonding at room temperature

We propose a fabrication process for a silicon on insulator (SOI) wafer with a diamond buried oxide (BOX) layer by combining nanodiamond-seeding deposition and a surface-activated bonding technique for high-frequency and power device applications. The diamond layer was deposited on a base wafer by the spin-coating of nanodiamonds and microwave-plasma-enhanced chemical vapor deposition. The thermal conductivity of this deposited diamond layer was three times that of a conventional SiO2 layer. A silicon wafer was then bonded to the diamond layer at room temperature in ultrahigh vacuum without forming any voids. Additionally, this SOI wafer was used to fabricate devices at 1000 °C. Therefore, we believe that this SOI wafer with a diamond BOX layer and its fabrication process are important for the realization of self-heating devices such as next-generation high-frequency and power devices.

Formation of SiO2 Dendritic Structures During Annealing of Silicon on Insulator Wafers

Silicon‐based sensors and actuators are the most prominent applications of silicon‐on‐insulator (SOI) microelectronic devices. The main reason for defects of these products is the low mechanical properties of the plates, due to their surface defects. To find out the causes of defects, studies are carried out by methods of measuring electron work function, scanning electron microscopy, atomic force, and secondary ion microscopy. It shows that in the case of defective SOI samples (doped by boron) on the silicon surface, there are silica fiber structures formed in zones having copper impurities. It is suggested that the fibrous SiO2 structure appeares as a result of the catalytic copper action on the process of silicon oxidation, causing the formation of polymeric fibers, at the end of which there are “caps” of copper. Presence of silica fibrous structure on the surface causes abnormally low electron work function values (<4.0 eV). Study of the heat treatment effect (room temperature ÷ 900 °C) of silicon wafers doped with boron and antimony impurities on the surface morphology made it possible to identify the changes that occur, to determine the roughness and the size of surface micro‐roughness, and to optimize the technological routes for MEMS manufacturing.

Extravillous trophoblast invasion is accelerated by WNT10B

Efficient steering of GeV-energy negatively charged particle beams was demonstrated to be possible with a new generation of thin bent silicon crystals. Suitable crystals were produced at the Sensor Semiconductor Laboratory of Ferrara starting from Silicon On Insulator wafers, adopting proper revisitation of silicon micromachining techniques such as Low Pressure Chemical Vapor Deposition, photolithography and anisotropic chemical etching. Mechanical holders, which allow to properly bend the crystal and to reduce unwanted torsions, were employed. Crystallographic directions and crystal holder design were optimized in order to excite quasi-mosaic effect along (1 1 1) planes. Prior to exposing the crystal to particle beams, a full set of characterizations were performed. Infrared interferometry was used to measure crystal thickness with high accuracy. White-light interferometry was employed to characterize surface deformational state and its torsion. High-resolution X-rays diffraction was used to precisely measure crystal bending angle along the beam. Manufactured crystals were installed and tested at the MAMI MAinz MIcrotron to steer sub-GeV electrons, and at SLAC to deflect an electron beam in the 1 to 10 GeV energy range.

Highly Ordered Microscale-Pyramidal-Structure-Arrayed Silicon Membranes for Filter Applications.

Microscale-pyramidal-structure-arrayed patterned silicon membranes are manufactured using semiconductor processes and potassium hydroxide (KOH) etching techniques for filter applications. The silicon nitride on silicon on the insulator wafer functions as a masking layer, and the roughness of the silicon (100) plane strongly depends on the etching temperature and KOH concentration. To fabricate the membrane filter, a series of dry and wet etching using 45 wt% KOH solutions at the constant temperature of 70 °C was performed. With the dry and wet etching, micro-pyramidal arrays with 300 μm top and 16-20 μm bottom opening sizes were created. The morphological structures were analyzed using scanning electron microscopy. The manufactured membranes were tested as optical directional filters and particle filters.

A 250-[formula omitted]m pitch 36-channel silicon photo multiplier array prototype using silicon on insulator technology

A 6×6 silicon photomultiplier (SiPM) array aimed at one-to-one coupling to a finely separated scintillator array was fabricated and characterized. All SiPMs were formed in the bulk substrate layer of a silicon on insulator (SOI) wafer for enabling future SiPMs which consists of 3-D integrated electronics without mechanical bonding. Each channel had a size of 250×250μm2 and was arranged for satisfying the counting-rate requirements of over 2 Mcps/mm2 in energy-resolvable X-ray photon counting computed tomography. To minimize the cost and complexity of the system’s back-end architecture and data acquisition, a novel two-dimensional coordinate readout was designed in anode terminals which contributes to the number of readout wires reduction without the position resolution degradation. As a feasibility study, the basic performance of a prototype analog SiPM array using the commercial SOI process was fabricated and characterized. Several features, such as a fast recovery time under 20 ns and a gain of 1×105 were within requirements to realize photon counting CT.

Performance study of optical resonator‐based filter architectures

A comparative study on characteristics and performance of optical ring resonator architectures, i.e. circular, racetrack, and triangular-shaped optical resonators, have been carried out here. Constituent material used for designing these resonators is an silicon on insulator wafer consisting of thin silicon (Si) layer on silica (SiO2) layer carried on a thick Si substrate having group index of 2.379. All the resonators are so designed that all provide equal free spectral range (FSR) of 25.2 THz. All these double-ring architectures have been analysed using delay line signal processing technique in z-domain and Mason's gain formula. FSR expansion has been achieved employing the Vernier principle. Various performance defining parameters have been also investigated.