Insulator Wafer Research Articles

A high-gain cladded waveguide amplifier on erbium doped thin-film lithium niobate fabricated using photolithography assisted chemo-mechanical etching

Abstract Erbium doped integrated waveguide amplifier and laser prevail in power consumption, footprint, stability and scalability over the counterparts in bulk materials, underpinning the lightwave communication and large-scale sensing. Subject to the highly confined mode in the micro-to-nanoscale and moderate propagation loss, gain and power scaling in such integrated devices prove to be more challenging compared to their bulk counterparts. In this work, a thin cladding layer of tantalum pentoxide (Ta2O5) is employed in the erbium doped lithium niobate (LN) waveguide amplifier fabricated on the thin film lithium niobate on insulator (LNOI) wafer by the photolithography assisted chemo-mechanical etching (PLACE) technique. Above 20 dB small signal internal net gain is achieved at the signal wavelength around 1532 nm in the 10 cm long LNOI amplifier pumped by the diode laser at ∼980 nm. Experimental characterizations reveal the advantage of Ta2O5 cladding in higher optical gain compared with the air-clad amplifier, which is further explained by the theoretical modeling of the LNOI amplifier including the guided mode structures and the steady-state response of erbium ions.

32 Element Piezoelectric Micromachined Ultrasound Transducer (PMUT) Phased Array for Neuromodulation

Interest in utilizing ultrasound (US) transducers for non-invasive neuromodulation treatment, including for low intensity transcranial focused ultrasound stimulation (tFUS), has grown rapidly. The most widely demonstrated US transducers for tFUS are either bulk piezoelectric transducers or capacitive micromachine transducers (CMUT) which require high voltage excitation to operate. In order to advance the development of the US transducers towards small, portable devices for safe tFUS at large scale, a low voltage array of US transducers with beam focusing and steering capability is of interest. This work presents the design methodology, fabrication, and characterization of 32-element phased array piezoelectric micromachined ultrasound transducers (PMUT) using 1.5 μm thick Pb(Zr0.52 Ti0.48)O3 films doped with 2 mol% Nb. The electrode/piezoelectric/electrode stack was deposited on a silicon on insulator (SOI) wafer with a 2 μm silicon device layer that serves as the passive elastic layer for bending-mode vibration. The fabricated 32-element PMUT has a central frequency at 1.4 MHz. Ultrasound beam focusing and steering (through beamforming) was demonstrated where the array was driven with 14.6 V square unipolar pulses. The PMUT generated a maximum peak-to-peak focused acoustic pressure output of 0.44 MPa at a focal distance of 20 mm with a 9.2 mm and 1 mm axial and lateral resolution, respectively. The maximum pressure is equivalent to a spatial-peak pulse-average intensity of 1.29 W/cm2, which is suitable for tFUS application.

Tronox site in Thann inaugurates sulfuric acid recycling unit

Efficient steering of GeV-energy negatively charged particle beams was demonstrated to be possible with a new generation of thin bent silicon crystals. Suitable crystals were produced at the Sensor Semiconductor Laboratory of Ferrara starting from Silicon On Insulator wafers, adopting proper revisitation of silicon micromachining techniques such as Low Pressure Chemical Vapor Deposition, photolithography and anisotropic chemical etching. Mechanical holders, which allow to properly bend the crystal and to reduce unwanted torsions, were employed. Crystallographic directions and crystal holder design were optimized in order to excite quasi-mosaic effect along (1 1 1) planes. Prior to exposing the crystal to particle beams, a full set of characterizations were performed. Infrared interferometry was used to measure crystal thickness with high accuracy. White-light interferometry was employed to characterize surface deformational state and its torsion. High-resolution X-rays diffraction was used to precisely measure crystal bending angle along the beam. Manufactured crystals were installed and tested at the MAMI MAinz MIcrotron to steer sub-GeV electrons, and at SLAC to deflect an electron beam in the 1 to 10 GeV energy range.

Submicron periodical poling by local switching in ion sliced lithium niobate thin films with a dielectric layer

Lithium niobate LiNbO3 (LN) on insulator wafers (LNOI) representing a submicron-thick LN film bonded to a SiO2 layer deposited on a thick LN substrate have been manufactured recently by ion slicing. Today, LNOI is one of the most promising materials for fabrication of various integrated optical devices, including waveguides, electro-optical modulators, and wavelength convertors, due to their high drop in refractive index at the interface between the film and the SiO2 layer. Creation of the stable domain structures with submicron periods in LNOI will improve the properties of nonlinear optical devices. Periodically poled LN with periods below 300 nm can be used to implement an optical parametric oscillator in the backward configuration. We have studied experimentally the ways to create the stripe domains and periodical domain structures in LNOI with a dielectric layer under the film by local switching. The identified scenarios of the domain evolution were attributed to the ineffective screening of depolarization field. We have shown that stripe domains and periodic domain structures can be produced by scanning with a biased tip only at temperatures above 80 °C. Periodical stable domain structures with periods down to 300 nm have been created.

Widely tunable silicon Raman laser

Stimulated Raman scattering is an effective means of wavelength conversion and can largely extend the operating spectral range of an optical source. We demonstrate a high-performance tunable Raman laser on a sub-micrometer-thick silicon on insulator wafer using a standard foundry process. The key feature to this laser is the use of a tunable coupling mechanism to adjust both pump and signal coupling coefficients in the ring cavity, allowing demonstration of laser emission over a large wavelength tuning range of 83 nm. This Raman laser demonstrates efficient (slope of up to 26% and a maximum pump-to-signal power conversion efficiency of 10%) on-chip nonlinear wavelength conversion. Our results indicate great promise for substantially increasing the optical spectral resources available on a silicon chip.

Detailing Influence of Contact Condition and Island Edge on Dual-Configuration Kelvin Pseudo-MOSFET Method

This article reports the influence of both contact condition and island edge on the electrical characteristics of the pseudo-metal-oxide-semiconductor-field-effect-transistor (pseudo-MOSFET) method. Our measurements reveal the sensitivity of the classical pseudo-MOSFET method on contact condition. We clarify that the presence of the OFF-state (an electrical characteristic) is controlled by modulating the surface condition of silicon on insulator wafer via chemical treatment. The Kelvin pseudo-MOSFET method reveals that surface condition, which impacts the barrier height for each carrier, can determine the electrical characteristics and the necessity to consider the influence of metal-semiconductor contact even if the probes are loaded at high pressure. The influence of the island edge is also analyzed. We clarify the necessity of using the dual-configuration Kelvin pseudo-MOSFET method to precisely offset the influence of the island edge. The influence of how the metal probes are placed on the specimen is discussed. To extract electrical parameters such as channel resistance and carrier mobility, we reveal that the probes must be placed symmetrically with respect to the specimen.

Cavity-BOX SOI: Advanced Silicon Substrate with Pre-Patterned BOX for Monolithic MEMS Fabrication

Several Silicon on Insulator (SOI) wafer manufacturers are now offering products with customer-defined cavities etched in the handle wafer, which significantly simplifies the fabrication of MEMS devices such as pressure sensors. This paper presents a novel cavity buried oxide (BOX) SOI substrate (cavity-BOX) that contains a patterned BOX layer. The patterned BOX can form a buried microchannels network, or serve as a stop layer and a buried hard-etch mask, to accurately pattern the device layer while etching it from the backside of the wafer using the cleanroom microfabrication compatible tools and methods. The use of the cavity-BOX as a buried hard-etch mask is demonstrated by applying it for the fabrication of a deep brain stimulation (DBS) demonstrator. The demonstrator consists of a large flexible area and precisely defined 80 µm-thick silicon islands wrapped into a 1.4 mm diameter cylinder. With cavity-BOX, the process of thinning and separating the silicon islands was largely simplified and became more robust. This test case illustrates how cavity-BOX wafers can advance the fabrication of various MEMS devices, especially those with complex geometry and added functionality, by enabling more design freedom and easing the optimization of the fabrication process.

High-Drain Field Impacting Channel-Length Modulation Effect for Nano-Node N-Channel FinFETs

Three dimensional (3-D) FinFET devices with an ultra-high Si-fin aspect ratio have been developed after integrating a 14Å nitrided gate oxide upon the silicon on insulator (SOI) wafers through an advanced CMOS logic platform. Under the lower gate voltage (VGS-VT) and the higher drain/source voltage VDS, the channel-length modulation (CLM) effect coming from the interaction impact of vertical gate field and horizontal drain field was increased and had to be revised well as the channel length L was decreased. Compared to the 28-nm MOSFETs, the interaction effect from the previous at the tested FinFETs on SOI substrate with the short-channel length L is lower than that at the 28-nm device, which means the interaction severity of both fields for nFinFETs is mitigated, but still necessary to be concerned.

Room-temperature bonded silicon on insulator wafers with a dense buried oxide layer formed by annealing a deposited silicon oxidation layer and surface-activated bonding

We propose a fabrication process for a silicon on insulator (SOI) wafer with an extremely thick buried oxide (BOX) layer for custom micro-electro mechanical systems (MEMS) devices. A BOX layer is generally formed by thermal oxidation above 800 °C. It is limited for this method to form an extremely thick layer of more than 10 μm. Thus, we attempted to deposit the BOX layer by chemical vapor deposition at 300 °C for a short time, followed by annealing at above 300 °C to make it denser. In addition, a silicon layer was bonded to the BOX layer at room temperature by surface activated bonding not to receive thermal stress. As a result, the bonding interface had no voids. The breakdown electric field of the BOX layer in the accidental B mode was improved by annealing. Therefore, SOI wafers fabricated by our method will be beneficial to next-generation MEMS device fabrication.

Resonant Sensing Element Realized as a Single Crystal Si Cantilever Actuated by Fringing Electrostatic Fields

We report on the fabrication and characterization of a generic, manufacturable, cantilever-type resonant sensing element, actuated by fringing electrostatic fields and fabricated from a silicon on insulator (SOI) wafer. The architecture of the electrode, designed to be thicker than the cantilever, was tailored to allow efficient electrostatic up-tuning of the beam’s frequency and enhancement of the device frequency to voltage/displacement sensitivity in the initial “as fabricated” configuration. The device is not prone to undesired pull-in instability and can be operated at large deflections, which increases the dynamic range. The multilevel structure was fabricated using a two-stage critically timed deep reactive ion etching (DRIE). The device was operated statically and dynamically by a combination of dc and ac voltages, and an increase of the resonant frequency with the increasing voltage/deflection was registered. Consistently with the model predictions, the experimental results suggest that this type of sensing element can be promising for implementation in a large variety of resonant, inertial, force or pressure sensors.

Highly Strained Silicon on Polymer Obtained By Temporary Polymer Wafer Bonding

Strain engineering can be called upon to tune the band structures of semiconductors. It is widely used in different types of microelectronics devices and it is expected to enable unprecedented responses in optoelectronics [1]. In the case of single crystal Silicon (sc-Si), several approaches have been proposed, relying either on the lattice mismatch inherent to hetero-epitaxial growth (Si on relaxed SiGe) or on substrate expansion (porous Si) [2, 3]. However, these methods are limited to bi-axial strain and by the maximum strain achievable in sc-Si thin film. We recently evaluated a method enabling to transfer a 200nm thick sc-Si film on a stretchable polymer substrate. Tensile tests proved that applying an external mechanical load on the substrate injected significant amounts of strain into sc-Si [4]. This work is focused on studying different parameters to improve the maximum strain in a Silicon On Polymer (SOP) stack obtained from a 200mm Silicon On Insulator (SOI) wafer using temporary polymer bonding.The overall fabrication process is described in figure 1(a). 2 × 24mm2 rectangles are defined using photolithography in a SOI thin film. The wafer is temporary bonded to a handling silicon substrate with a 40µm thick glue layer. Then, the backside of the SOI is removed with mechanical grinding and selective chemical etching. Finally, the sc-Si thin film is transferred to a 230µm thick flexible substrate thanks to a release layer between the glue and the sc-Si layer. The substrate is cut into tensile test samples as described in figure 1(a).In a previous study we have shown that a 200nm thick sc-Si film could be uniaxialy strained up to 1.5% along the [110] direction [4]. In the present work, we quantify the impact of strain orientation, sc-Si film thickness and pattern edge roughness on maximum uniaxial strain. In order to change the sc-Si film thickness a dry etching step was used after removing the backside of the SOI ubstrate. A soft lithography mask and a standard chrome 1X lithography mask were compared for the fabrication of rectangles. To achieve even smoother pattern edges, TetraMethylAmmonium Hydroxide (TMAH) etching was also used (for 90 minutes in a 25 %wt solution at 80◦C) on a patterned SOI with a silicon oxide layer as a hard mask. Resulting samples were tested on a uniaxial tensile stage coupled to a Raman spectrometer, giving us access simultaneously to the sample macroscopic strain and the silicon local strain.Tensile test results are summarized in figure 1(b). Reducing the thickness of the sc-Si did not improve the strain limit while better edges definitions did. Indeed, using TMAH, uniaxial strains up to 3% along [100] were reached in a 200nm thick sc-Si film on a flexible polymer substrate. These results are highly encouraging for the development of films with a wide range of strain. Furthermore, this method is easily transferable to other materials such as AlN or Ge.

On-chip erbium-doped lithium niobate microcavity laser

The commercialization of lithium niobate on insulator (LNOI) wafer has sparked significant on-chip photonic integration application due to its remarkable photonic, photoacoustic, electro-optic and piezoelectric nature. A variety of on-chip LNOI-based optical devices with high performance has been realized in recent years. Here we developed 1 mol\% erbium-doped LN crystal and its LNOI wafer, and fabricated an erbium-doped LNOI microdisk with high quality ($ \sim $ 1.05$\times 10^{^5}$ ). C-band laser emission with $ \sim $1530 nm and $ \sim $1560 nm from the high-Q erbium-doped LNOI microdisk was demonstrated both with 974 nm and 1460 nm pumping, and the latter has better thermal stability. This microlaser would play an important role in the photonic integrated circuits of lithium niobate platform.

Estimation of the mechanical stiffness constant of MEMS-based parallel-plate micro-actuators

The fabrication and testing of a parallel plate MEMS electrostatic micro-actuator is reported. The device consists of stationary bulk silicon and movable membrane chips with three spring-like x-beam configurations fabricated from a silicon on insulator (SOI) wafer. A SU-8 photoresist layer was deposited on the stationary chip to act as a spacer since its thickness determines the electrostatic force that can be applied. This in turn has an effect on the displacement of the micro-actuator. We investigated the effects of the applied voltage on the displacement of movable x-beam membranes for different arm designs with similar surface areas. We achieved maximum stable displacements of 8.75 µm and 9.89 µm for spacer thicknesses of 28 µm and 33 µm at 95 VDC and 128 VDC, respectively, for a serpentine arm design. Beyond these voltages, we found the displacement of the micro-actuator tended to be non-uniform and unstable. We also estimated the mechanical stiffness constants of our x-beam designs from the snap-in conditions. Our estimates for various spacer thicknesses were within 5% of one another.

Response analysis of MEMS based high-g acceleration threshold switch under mechanical shock

Failures of MEMS devices under shock are due to the overlap of the static and moving parts. The shock response of the microstructure under mechanical shock is investigated in this paper. This work presents modelling and simulation of the microstructures such as microcantilever, fixed–fixed flexure and serpentine structure and is further extended to optimize the response of high-g acceleration threshold switch under mechanical shock. The latching threshold for the high-g acceleration switch is estimated using the geometrical structure. The natural frequency of the serpentine spring-mass structure is selected to achieve the required displacement for latching. The dimensions of the switch are optimized in accordance with the natural frequency and to meet the requirement of latching for a given shock. The switch is fabricated on silicon on insulator wafer with a deep reactive ion etching process. The switch is tested on the static mechanical shock of 3500 g and shows a good agreement between analytical, numerical and experimental results.

Understanding the effect of confinement in scanning spreading resistance microscopy measurements

Scanning spreading resistance microscopy (SSRM) is a powerful technique for quantitative two-and three-dimensional carrier profiling of semiconductor devices with sub-nm spatial resolution. However, considering the sub-10 nm dimensions of advanced devices and the introduction of three-dimensional architectures like fin field effect transistor (FinFET) and nanowires, the measured spreading resistance is easily impacted by parasitic series resistances present in the system. The limited amount of material, the presence of multiple interfaces, and confined current paths may increase the total resistance measured by SSRM beyond the expected spreading resistance, which can ultimately lead to an inaccurate carrier quantification. Here, we report a simulation assisted experimental study to identify the different parameters affecting the SSRM measurements in confined volumes. Experimentally, the two-dimensional current confinement is obtained by progressively thinning down uniformly doped blanket silicon on insulator wafers using scalpel SSRM. The concomitant SSRM provides detailed electrical information as a function of depth up to oxide interface. We show that the resistance is most affected by the interface traps in case of a heterogeneous sample, followed by the intrinsic resistance of the current carrying paths. Furthermore, we show that accurate carrier quantification is ensured for typical back contact distances of 1 μm if the region of interest is at least nine times larger than the probe radius.

An On-Chip Micromachined Test Structure to Study the Tribological Behavior of Deep-RIE MEMS Sidewall Surfaces

An on-chip micro-mechanical test structure is presented to investigate the tribological behavior of deep reactive ion etching (DRIE) sidewall surfaces of microelectromechanical systems (MEMS) devices. The proposed test structure is fabricated on silicon on insulator (SOI) wafer using a standard surface micromachine process. Test structure consists of two orthogonally placed electrostatic comb-drive actuators, one is used to align a contact with the friction surfaces under a certain normal load, and another one is used to generate the tangential motion on contacted sidewall surfaces. To assess the frictional behavior of DRIE sidewall surfaces, both static and dynamic friction coefficients were studied for different DRIE process parameters. Wear analysis was carried out to extract the performance and reliability of MEMS sidewall surfaces during their operation. From the experiment results, it is found that with the increment of normal load, the static friction coefficient exhibits a nonlinear dependence, and however, it has less effect on the dynamic friction coefficient. DRIE process parameters have a significant influence on static and dynamic friction coefficients, i.e., variation in asperity size changes the real contact area between the contact pairs during their operation. From the wear analysis, it is found that the friction coefficient was very high initial value, then it drops with each subsequent cycle for a few cycles and finally reaches steady-state value.

Fabrication of silicon on insulator wafer with silicon carbide insulator layer by surface-activated bonding at room temperature

We propose a process for the fabrication of a silicon-on-insulator (SOI) wafer with a silicon carbide (SiC) insulator layer by combining plasma-enhanced chemical vapor deposition and surface-activated bonding without thermal stress to obtain sufficient thermal conductivity for self-heating power and high-frequency device applications. The thermal conductivity of the deposited SiC layer is twice that of a silicon dioxide (SiO2) layer, and the breakdown electric field of this layer is 10–11 MV cm−1, the same as that of a SiO2 layer. In addition, the bonding interface between the silicon layer and the deposited SiC insulator layer has no voids or punch-out dislocations. Therefore, the SOI wafer with a SiC layer has high thermal conductivity and breakdown electric field; this SOI wafer and its fabrication process will be important for the realization of next-generation self-heating devices such as power and high-frequency devices.

Domain structure formation by local switching in the ion sliced lithium niobate thin films

The creation of the periodical domain patterns with a submicron period in lithium niobate on insulator (LNOI) wafers is a key problem for nonlinear-optical applications, including second harmonic generation, backscattering optical parametric oscillator, etc. We have experimentally studied the domain formation and evolution during local polarization reversal in Z+ LNOI wafers with a metal bottom electrode. It has been shown that domain growth occurs by the formation of the spikes at the charged domain wall (CDW). The complicated shape of isolated domains with a jagged CDW has been revealed. The obtained weak domain–domain interaction has been attributed to effective bulk screening by charge injection. The revealed dependence of the domain sizes on humidity caused by the adsorbed water layer should be taken into account during periodical poling.

Modelling of Phosphorus and Boron Doping Concentration on SOI Wafer Based Diffusion Process

High concentration of Boron and Phosphorus elements are required in diffusion process during the fabrication of semiconductor devices such as diode and transistor based on Silicon On Insulator (SOI) wafer. Achieving high level of these elements’ concentration is the entry point for further research in the field of electronics. For this reason, the concentration of the both elements was tested by flowing Boron and Phosphorus gas with flow rate of 1.5 litre per minute into the Nitrogen furnace for 5 minutes towards the surface of the SOI wafer samples at temperatures of 880, 900 and 950 degrees Celsius. This test was carried out at Michiharu Tabe Laboratory, Research Institute of Electronics, Shizuoka University, Hamamatsu, Japan. Furthermore, the resistivity measurements of  samples with Boron and Phosphorus doping were carried out. The results of resistivity were then converted to obtain the concentrations of Boron and Phosphorus on the surface of SOI wafer sample. From the concentration and temperature data, it is obtained the modelling of concentration to temperature function for Boron and Phosphorus. The modelling results show that there is a linear correlation between high concentrations of Boron and Phosphorus to temperature.

A Flow-Through Microfluidic Relative Permittivity Sensor

In this paper, we present the design, simulation, fabrication and characterization of a microfluidic relative permittivity sensor in which the fluid flows through an interdigitated electrode structure. Sensor fabrication is based on an silicon on insulator (SOI) wafer where the fluidic inlet and outlet are etched through the handle layer and the interdigitated electrodes are made in the device layer. An impedance analyzer was used to measure the impedance between the interdigitated electrodes for various non-conducting fluids with a relative permittivity ranging from 1 to 41. The sensor shows good linearity over this range of relative permittivity and can be integrated with other microfluidic sensors in a multiparameter chip.