Insulator Semiconductor Field Effect Transistors Research Articles

Analytical model and simulation study of a novel enhancement-mode Ga2O3 MISFET realized by p-GaN gate

In this paper, we propose a novel junction-less Ga2O3 metal–insulator–semiconductor field effect transistor (MISFET) with a p-GaN gate, named p-GaN Ga2O3-MISFET. A heavily doped thin layer p-GaN is set in the trench gate region to deeply deplete the n-Ga2O3 channel region owing to the high work function of the p-GaN. Thus, a high threshold voltage (V TH) and breakdown voltage (BV) can be obtained even with a wide-fin design and low interface charge density (n int), which ensures easy fabrication and a stable V TH. Analytical modeling and experimentally calibrated technology computer aided design (TCAD) simulations confirm that with the increase of fin width (W Fin) from 0.1 μm to 0.5 μm, the V TH of the p-GaN Ga2O3-MISFET varies from 3.2 V to 2.4 V with n int = −1 × 1011 cm−2, which is always about 2.2 V higher than those of conventional junction-less Ga2O3 MISFETs (CJL-MISFET). In addition, the BV of the CJL-MISFET decreases from ∼3400 V to ∼45 V with increasing W Fin due to soft breakdown, while the BV of the p-GaN MISFET only decreases to 2800 V due to the enhanced electric field at the corner of the trench gate. Moreover, the activation energy and doping concentration (when larger than 3 × 1019 cm−3) of p-GaN barely affect the V TH. Even so, a high V TH remained in a common range of interface charge (from 1 × 1013 cm−2 to 2 × 1013 cm−2) at the p-GaN/Al2O3 interface.

Фоточувствительность полевого транзистора металл-диэлектрик-полупроводник на основе пленки PbSnTe:In с составом вблизи инверсии зон

A prototype of a metal–insulator–semiconductor field-effect transistor based on PbSnTe:In/(111)BaF2 film with an Al2O3 gate dielectric was designed for the first time. With the gate voltage applied in the range – 7.7 V < Ugate < +7.7 V the relative modulation in the drain-source current Ids/Ids attained near five-fold change at T = 4.2 K. When illuminated with rela-tively low (~100 photon/s) fluxes, negative photoconductivity was detected accompanied with a decrease in Ids by ~104 times and a simultaneous decrease in Ids by ~103 times or even more. The estimated detectivity was about 71016 cmHz0.5W-1 at a wavelength  about 25 micron with the accumulation time about 0.5 s. A qualitative model is discussed which assumes the ex-istence of deep traps and a photo-capacitance effect.

Recessed-gate AlGaN/GaN MIS-FETs with dual 2DEG channels

In this study, a normally-on AlGaN/GaN metal–insulator-semiconductor high electron mobility transistor (MIS-HEMT) and a normally-off AlGaN/GaN metal–insulator-semiconductor field-effect transistor (MIS-FET) with recessed MIS gate are fabricated by dual-channel epitaxy structure. The recessed region is cleaned by dipping it into diluted buffered oxide etch (BOE), HCl, and tetramethylammonium hydroxide (TMAH) solutions. After cleaning, a 20 nm Al2O3 is deposited by atomic layer deposition (ALD). Then, the post-deposition annealing is executed. Non-recessed MIS-HEMT demonstrates a threshold voltage of −9.81 V, a high drain current of 660.76 mA mm−1, and a small on-resistance of 6.47 Ω mm. Recessed gate MIS-FET shows a positive threshold voltage of 1.46 V with a drain current of 144.81 mA mm−1. In addition, the devices present a high gate breakdown voltage of 26.5 V by non-recessed MIS-HEMT and 18.5 V by recessed MIS-FET. Both devices show a low I–V hysteresis under double sweep I D–V GS measurement.

Self-Aligned Organic Metal–Semiconductor Field-Effect Transistor

We propose the design and fabrication of a coplanar electrode structure for an organic metal–semiconductor field-effect transistor (OMESFET), with the gate electrode self-aligned between the source and drain electrodes. We first used nanoimprint lithography (NIL) to define a channel area of the device on a patterned metal, and then used chemical wet etching to create the source and drain electrodes by removing the metal in the channel area. After the wet etching, the gate electrode was deposited in the channel area. The organic semiconductor was then deposited to cover the patterned electrodes. The rectifying response and the device characteristics prove that the self-aligned device is a functional OMESFET. In this experiment, we also demonstrated that the self-aligned OMESFET has lower driving voltages and smaller subthreshold swing (SS) than that of a conventional organic metal–insulator–semiconductor field-effect transistor (OMISFET). Compared with the most common OMESFET structure, this self-aligned coplanar structure effectively eliminates the overlapping area between the gate and source/drain electrodes commonly seen in currently reported OMESFETs, which means that this self-aligned device structure reduces the parasitic capacitance, theoretically allowing the transistor to have a higher cutoff frequency. These features render our proposed OMESFET devices more favorable for low-power and high-frequency organic circuit applications.

Effect of Gate Dielectric Material on the Electrical Properties of MoSe2-Based Metal–Insulator–Semiconductor Field-Effect Transistor

In this study, we fabricated metal–insulator–semiconductor field-effect transistors (MISFETs) based on nanolayered molybdenum diselenide (MoSe2) using two insulator materials, silicon dioxide (SiO2) and silicon nitride (SiN). We performed morphological and electrical characterizations in which the devices showed good electronic performance, such as high mobility and high Ion/Ioff ratios exceeding 104. The subthreshold swing (ss) was somewhat high in all devices owing to the dimensions of our devices. In addition, the transfer curves showed good controllability as a function of gate voltage. The photogating effect was weakened in MoSe2/SiN/Si, indicating that SiN is a good alternative to silicon oxide as a gate dielectric material.

High-performance normally-off recessed tri-gate GaN MIS-FETs in micrometer scale

In this study, a normally-off AlGaN/GaN metal–insulator–semiconductor field-effect transistor (MIS-FET) based on the combination of tri-gate and recessed MIS gate is fabricated and characterized. The recessed tri-gate MIS-FET is manufactured by micro-level trenches, defining the fin-shaped channel and improving the gate control capability. The recessed surface is cleaned by a diluted buffered oxide etch, HCl solution, and tetramethylammonium hydroxide treatment before a 20 nm Al2O3 deposition by atomic layer deposition. After deposition, post-deposition annealing was carried out. Recessed tri-gate MIS-FET demonstrates a high threshold voltage of 3.1 V, a high drain current of 1121 mA mm−1, and an on/off current ratio of 2 × 108. A smaller on-resistance of 5.4 Ω mm compared with recessed planar MIS-FET of 12.7 Ω mm is achieved. Besides, the devices show a low I–V hysteresis. All experimental results confirm micro-level trenches realize the advantages of the recessed tri-gate structures, which supports a promising technique to pursue the normally-off operation of GaN high electron mobility transistors.

Modeling and characterization of photovoltaic and photoconductive effects in insulated-gate field effect transistors under optical excitation

Under optical illumination of metal–insulator-semiconductor field effect transistors with insulated gate structure (MISFETs including MOSFETs and TFTs), photo-generated electron-hole pairs (ehp’s) cause the photovoltaic effect (PVE) and the photoconductive effect (PCE) in the electrical characteristics of MISFETs. In the modeling and characterization of MISFETs under optical excitation for both optical sensing and/or electro-optical characterization of traps through photonic C-V and I-V responses, it is necessary to separate the PVE from the PCE in MISFETs. In this letter, we report the modeling and separate characterization of the PVE from the PCE in MISFETs applicable to MOSFETs and TFTs. We confirmed the proposed model and the technique through experimental results adopting the different substrate contact configurations and optical power of the device under characterization. As a result, the effective surface potential change for the PCE (VPCE) and the effective substrate potential change for the PVE (VPVE) could be quantitatively extracted.

Normally-off sputtered-MoS2 nMISFETs with TiN top-gate electrode all defined by optical lithography for chip-level integration

We demonstrate chip-level integrated n-type metal–insulator–semiconductor field effect transistors with a sputtered molybdenum disulfide (MoS2) thin channel and titanium nitride top-gate electrode, all defined by optical lithography. The devices successfully exhibit a normally-off operation and the highest off-voltage. This is achieved by the single dielectric layer and forming gas annealing, which reduce the positive fixed charges in aluminum oxide (Al2O3) film and interface trap densities between the MoS2 and Al2O3 films, respectively. These normally-off MISFETs are suitable for internet-of-things edge devices with low energy consumption using two-dimensional materials in the future.

TCAD simulation of a breakdown-enhanced double channel GaN metal–insulator–semiconductor field-effect transistor with a P-buried layer

This paper proposes a new breakdown-enhanced gallium nitride (GaN) metal–insulator–semiconductor field-effect transistor (MISFET) with the architecture of a double channel and a P-buried layer, i.e. DCP-MISFET. The lower barrier and lower channel are connected to the drain, and the lower two-dimensional electron gas can improve the device electric field distribution between the gate and drain, achieving an enhanced breakdown voltage. At the same time, the P-buried layer below the gate field plate can reduce the peak electric field around the gate field plate. The proposed simulated device with LGD = 15 μm presents an excellent breakdown voltage of 2373 V. In addition, the ON-resistance of 15.07 s Ω mm and Baliga’s figure of merit of 3.736 GW cm−2 are achieved in the optimized DCP-MISFET. Compared with the breakdown voltage of 1547 V of the optimized field plate conventional GaN MISFET, the proposed device increases the breakdown voltage by 53.39% and the Baliga’s figure of merit is enhanced by 133.89%.

Ambipolar Charge Transport in Two-Dimensional WS2 Metal-Insulator-Semiconductor and Metal-Insulator-Semiconductor Field-Effect Transistors.

Two-dimensional (2D) materials with ambipolar transport characteristics have attracted considerable attention as post-complementary metal-oxide semiconductor (CMOS) materials. These materials allow for electron- or hole-dominant conduction to be achieved in a single channel of the field-effect transistors (FETs) without an extrinsic doping. In this study, all-2D metal-insulator-semiconductor (MIS)-based devices, which were composed of all-2D graphene, hexagonal boron nitride, and WS2, exhibited ambipolar and symmetrical transport characteristics with a low surface state density (Dit,min ≈ 7 × 1011 cm-2·eV-1). Hole- or electron-dominant inversion under the influence of electrostatic doping was obtained in a WS2-based 2D capacitor up to a frequency range of 1 MHz. n- and p-channel conductions with enhancement-mode operations were selectively realized in a single MISFET, which presented a current on/off ratio of >106 and high field-effect mobility (μe = 58-67 cm2/V·s and μh = 19-30 cm2/V·s). Furthermore, a monolithic CMOS-like logic inverter, which employed a single WS2 flake, exhibited a high gain of 78. These results can be used to reduce the footprints of the device architectures and simplify the device fabrication processes of next-generation CMOS integrated circuits.

Field effect transistor with thin AlOxNy film as gate dielectric

PurposeThe purpose of this study is to directly measure and determine the Si/SiO2/AlOxNy interface state density on metal insulator semiconductor field effect transistor (MISFET) structures. The primary advantage of using aluminum oxynitride (AlOxNy) is the perfectly controlled variability of the properties of these layers depending on their stoichiometry, which can be easily controlled by the parameters of the magnetron sputtering process. Therefore, a continuous spectrum of properties can be achieved from the specific values for oxide to the specific ones for nitride, thus opening a wide range of applications in high power, high temperature and high frequency electronics, optics and sensors and even acoustic devices.Design/methodology/approachThe basic subject of this study is n-channel transistors manufactured using silicon with 50-nm-thick AlOxNy films deposited on a silicon dioxide buffer layer via magnetron sputtering in which the gate dielectric was etched with wet solutions and/or dry plasma mixtures. Furthermore, the output, transfer and charge pumping (CP) characteristics were measured and compared for all modifications of the etching process.FindingsAn electrical measurement of MISFETs with AlOxNy gate dielectrics was conducted to plot the current-voltage and CP characteristics and examine the influence of the etching method on MISFET parameters.Originality/valueIn this report, a flat band and threshold voltage and the density of interface traps were determined to evaluate and improve an AlOxNy-based MISFET performance toward highly sensitive field effect transistors for hydrogen detection by applying a Pd-based nanocrystalline layer. The sensitivity of the detectors was highly correlated with the quality of the etching process of the gate dielectrics.

650 mW/mm output power density of H‐terminated polycrystalline diamond MISFET at 10 GHz

In this work, metal–insulator–semiconductor field effect transistors (MISFET) with gate length of 350 nm were fabricated on hydrogen-terminated polycrystalline diamond by a self-aligned process. Aluminium film with thickness of 2 nm was evaporated on the sample and formed self-oxidised alumina to act as the gate dielectric. The devices show good direct current and radio frequency performances with a maximum frequency of oscillation (f max) of 34 GHz and continuous-wave output power density of 650 mW/mm at 10 GHz.

Influence of AlN etching process on MISFET structures

Purpose The purpose of this paper is to present the influence of gate dielectric etching on obtained MISFET (metal insulator semiconductor field effect transistor) structures. Because of its properties, aluminum nitride (AlN) layers can be successfully used in a large area of applications. In addition, AIN has a wide bandgap (6.2eV) and high thermal conductivity (3.2 W/cm * K). Its melting temperature is greater than 2,000°C. The relative permittivity is about 9. All these features (especially high power, high temperature and high-frequency) make AlN a useful material in the fields of electronic, optical and acoustic applications. Design/methodology/approach To fabricate n-channel transistors, silicon technology was used. The 50-nm thick AlN films were deposited using the magnetron sputtering. After preparation of SiO2/AlN stack as the gate dielectric, the optimization processes of dry etching in plasma environment by Taguchi method were realized. In the next step, three methods of AlN etching were selected and used to MISFET device fabrication. Atomic force microscopy and scanning electron microscopy allowed to surfacing of the state observation after etching process. The current–voltage (I–V) output and transfer characteristics of structures with modified etch technology were measured. Keithley SMU 236/237/238 measurement set was used. Findings In this research work, a method of AlN etching in a field effect transistor technology was developed and improved. Current−voltage characteristics of obtained MISFET structures were measured and compared. Influence of etching procedure on transistors properties was examined. Originality/value The obtained results allow improving the MISFET technology based on AlN film as a gate dielectric. The complete research work will allow using the developed technologies to implement in highly sensitive ion-sensitive field effect transistor (ISFET) structures in the future. The improvement of the etching element in the technology strongly influences the detection capabilities and operating range of the transistor.

Modeling and Simulation Study of Reduced Self-Heating in Bottom-Gate β-Ga2O3 MISFETs with a h-BN Gate Insulator

Beta-gallium oxide (β-Ga2O3) is an emerging ultra-wide bandgap semiconductor material for high-power devices. However, one of the major drawbacks is the low thermal conductivity resulting in poor heat dissipation, and the so-called self-heating effect reduces carrier mobility and drain current degradation, and even causes a device reliability issue. Here, we propose a bottom-gate β-Ga2O3 field-effect transistor with a hexagonal boron-nitride (h-BN) gate-insulator and investigate the self-heating effect in comparison with an aluminum oxide (Al2O3) insulator using physics-based TCAD simulations. The h-BN with high thermal conductivity reduces the lattice temperature of the β-Ga2O3 channel and decreases drain current degradation. Furthermore, as the thickness of the insulator decreases below 50 nm and the channel length is scaled down to 5 μm, the reduced self-heating effect becomes more prominent. The results imply that the highly thermal-conductive h-BN insulator is promising for achieving high performance β-Ga2O3 metal insulator semiconductor field-effect transistor (MISFET) with the bottom-gate configuration.

A model for nonvolatile p-channel metal–ferroelectric–metal–insulator–semiconductor field-effect transistors (MFMIS FETs)

An improved theoretical model for metal–ferroelectric–metal–insulator–semiconductor field-effect transistors (MFMIS FETs) is presented. The basic theory describing the ferroelectric behavior is replaced by the dipole switching theory (DST) because of its deeper physical meaning and its ability to account for the history-dependent electric field effect of the ferroelectric. Using the combination of DST and the theory of series capacitances, the capacitance–voltage (C–V) characteristic of the MFMIS structure is simulated, while the combination of the DST with Pao and Sah’s double integral enables the simulation of the drain current–gate voltage (ID–VGS) and drain current–drain voltage (ID–VDS) characteristics. The good agreement between the simulation and experimental results confirms the validity of this model. The effects of the area ratio AF/AM on the C–V, ID–VGS, and ID–VDS characteristics are further provided by the model. The simulation results indicate that the applied voltage and ID ON/OFF ratio decrease while the memory window widens as the area-ratio increases. This work is expected to help direct the design and fabrication of MFMIS-based devices.

200°C normally off AlGaN/GaN MISFET with 321 mA/mm drain current density and 1055 V breakdown voltage

A high-performance normally off recess-gated aluminium gallium nitride (AlGaN)/GaN metal–insulator–semiconductor field-effect transistor (MISFET) is successfully demonstrated with operation temperature of 200°C which was fabricated by using a self-terminating gate recess etching technique. At 200°C, by employing a high-quality aluminium oxide/silicon nitride bilayer as gate dielectrics, the fabricated device exhibits a high threshold voltage of 4.5 V, a high drain current density of 321 mA/mm, a low off-state leakage current of 20 μA/mm as well as a high on/off current ratio of ∼106. Furthermore, a high forward gate breakdown voltage of 23.6 V (∼7.9 MV/cm) and an off-state breakdown voltage as high as 1055 V are obtained in the fabricated device, both of which, as far as it is known, is the highest reported value in normally off GaN devices operated at 200°C. The high threshold voltage, large drain current density, low off-state leakage current, high gate breakdown voltage as well as high off-state breakdown voltage make this normally off recess-gated AlGaN/GaN MISFET very suitable for high-temperature power switch applications.

Hydrogen effects on AlGaN/GaN MISFET with LPCVD-SiNx gate dielectric

In this work, the effects of hydrogen on an AlGaN/GaN metal insulator semiconductor field effect transistor (MISFET) with SiNx gate dielectric were investigated. It is found that after hydrogen exposure, (1) the AlGaN/GaN MISFET exhibits better DC performance with larger maximum transconductance, (2) the gate lag phenomenon is effectively suppressed and (3) the 1/f noise performance is improved with lower noise magnitude. These results are different from previous observations in other III–V semiconductor devices. Based on the theoretical analysis by space charge limited current and low-frequency noise models, we propose that the hydrogen treatment induces hydrogen incorporation into SiNx, which could passivate the defect centers. These findings demonstrate the high hydrogen tolerance of AlGaN/GaN MISFETs.

Controlling the threshold voltage of β-Ga2O3 field-effect transistors via remote fluorine plasma treatment

The threshold voltage of β-Ga2O3 metal–insulator–semiconductor field-effect transistors is controlled via remote fluorine plasma treatment, enabling an enhancement-mode operation under double gate condition.

Van der Waals junction field effect transistors with both n- and p-channel transition metal dichalcogenides

Two-dimensional (2D) transition metal dichalcogenides (TMDs)-based van der Waals (vdW) PN junctions have been used for heterojunction diodes, which basically utilize out-of-plane current across the junction interface. In fact, the same vdW PN junction structure can be utilized for another important device application, junction field effect transistors (JFETs), where in-plane current is possible along with 2D–2D heterojunction interface. Moreover, the 2D TMD-based JFET can use both p- and n-channel for low voltage operation, which might be its unique feature. Here we report vdW JFETs as an in-plane current device with heterojunction between semiconducting p- and n-TMDs. Since this vdW JFET would have low-density traps at the vdW interface unlike 2D TMD-based metal insulator semiconductor field effect transistors (MISFETs), little hysteresis of 0.0–0.1 V and best subthreshold swing of ~100 mV/dec were achieved. Easy saturation was observed either from n-channel or p-channel JFET as another advantage over 2D MISFETs, exhibiting early pinch-off at ~1 V. Operational gate voltage for threshold was near 0 V and our highest mobility reaches to ~>500 cm2/V·s for n-channel JFET with MoS2 channel. For 1 V JFET operation, our best ON/OFF current ratio was observed to be ~104.

An atom-to-circuit modeling approach to all-2D metal\u2013insulator\u2013semiconductor field-effect transistors

Vertical stacking of heterogeneous two-dimensional (2D) materials has received considerable attention for nanoelectronic applications. In the semiconductor industry, however, the process of integration for any new material is expensive and complex. Thus, first principles-based models that enable systematic performance evaluation of emerging 2D materials at device and circuit level are in great demand. Here, we propose an ‘atom-to-circuit’ modeling framework for all-2D MISFET (metal–insulator–semiconductor field-effect transistor), which has recently been conceived by vertically stacking semiconducting transition metal dichalcogenide (e.g., MoS2), insulating hexagonal boron nitride and semi-metallic graphene. In a multi-scale modeling approach, we start with the development of a first principles-based atomistic model to study fundamental electronic properties and charge transfer at the atomic level. The energy band-structure obtained is then used to develop a physics-based compact device model to assess transistor characteristics. Finally, the models are implemented in a circuit simulator to facilitate design and simulation of integrated circuits. Since the proposed modeling framework translates atomic level phenomena (e.g., band-gap opening in graphene or introduction of semiconductor doping) to a circuit performance metric (e.g., frequency of a ring oscillator), it may provide solutions for the application and optimization of new materials.