Insulator Metal Oxide Semiconductor Research Articles

Improving Short Channel Effects by Reformed U-Channel UTBB FD SOI MOSFET: A Feasible Scaled Device

U-channel ultra-thin body and buried oxide (U-UTBB) Silicon On Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) present unique features which are simple, high-performance, area efficient, and compatible with CMOS technology. In this paper, we present the electrical characteristics of a U-UTBB SOI MOSFET with reforming the U-channel. This proposed symmetrical and planar device is initiated by removing two spacers around the recessed metal gate in the U-channel MOSFET. Hence, it causes to increase the overall channel length at the firm metal gate space along with saving area. As it has confirmed by two-dimensional and two-carrier device simulation results, the proposed structure which is termed Reformed U-UTBB (R-U-UTBB) fully depleted SOI MOSFET exhibits advantages in the device performance focusing on short channel effects (SCEs) factors including the sub-threshold slope, the drain induced barrier lowering (DIBL), and the threshold voltage roll-off. Leakage current and on-to-off current ratio are studied as well which all of them show the superiority of proposed structure compared with the U-UTBB FD SOI MOSFET and a conventional UTBB (C-UTBB) FD SOI MOSFET. In addition, the effects of process-induced variations have investigated by varying buried oxide thickness, top silicon thickness, channel thickness, substrate doping, and oxide thickness on threshold voltage, sub-threshold slope, and drain induced barrier lowering (DIBL).

Impact of Structural Aspect, Metal Gate and Channel Material on UTB-SOI-MOSFET

Ultra Thin Body Silicon on Insulator Metal Oxide Semiconductor Field Effect Transistors (UTB-SOI-MOSFETs) provide better immunity to Short Channel Effects (SCEs). But the behaviour changes at miniaturization and still the many unexplored effects need to be analysied. Here in this paper, Drain Induced Barrier Lowering (DIBL) and sub-threshold Slope (SS) variation of a n-channel UTB-SOI-MOSFET have been analyzed by changing the device structural aspects like gate length (LG), BOX thickness (tBOX) and Silicon film thickness (tSi). Also, the effect of intrinsic parameters as metal gate work function and channel material variation on DIBL and sub-threshold Slope (SS) variation has been analyzed.

Improved interfacial properties of HfGdON gate dielectric Ge MOS capacitor by optimizing Gd content**Project supported by the National Key Research and Development Program of China (Grant No. 2018YFB2200500) and the National Natural Science Foundation of China (Grant Nos. 61851406 and 61274112).

High-quality dielectric/Ge interface and low gate leakage current are crucial issues for high-performance nanoscaled Ge-based complementary metal–oxide–semiconductor (CMOS) device. In this paper, the interfacial and electrical properties of high-k HfGdON/LaTaON stacked gate dielectric Ge metal–oxide–semiconductor (MOS) capacitors with different gadolinium (Gd) contents are investigated. Experimental results show that when the controlling Gd content is a suitable value (e.g., ∼ 13.16%), excellent device performances can be achieved: low interface-state density (6.93 × 1011 cm−2 · eV−1), small flatband voltage (0.25 V), good capacitance–voltage behavior, small frequency dispersion, and low gate leakage current (2.29× 10−6 A/cm2 at Vg = Vfb + 1 V). These could be attributed to the repair of oxygen vacancies, the increase of conduction band offset, and the suppression of germanate and suboxide GeOx at/near the high k/Ge interface by doping suitable Gd into HfON.

Impact of structural parameters on DC performance of recessed channel SOI-MOSFET

With the concept of groove gate and implementing the idea of silicon on insulator (SOI), a new analytical model is developed for the rectangular recessed channel silicon on insulator (RRC-SOI) metal oxide semiconductor field effect transistor (MOSFET). This analytical model is formulated using 2D Poisson's equation and develops a compact equation for threshold voltage using minimum surface potential. This paper analyses the effect of negative junction depth (NJD) on device parameters, such as minimum surface potential, threshold voltage, sub-threshold slope (SS), and drain induced barrier lowering (DIBL). The impact of oxide thickness variation on the above parameters has also been evaluated. Further, the linearity performance in terms of figure of merits (FOM) and device parameters like drain current and trans-conductance of the proposed model is compared with the simulated results of rectangular recessed channel (RRC) MOSFET. The validity of the proposed model has been verified with simulation results performed on Sentaurus TCAD device simulator.

Inversion Charge Boost and Transient Steep-Slope Induced by Free-Charge-Polarization Mismatch in a Ferroelectric-Metal–Oxide–Semiconductor Capacitor

In this letter, the transient behavior of a ferroelectric (FE) metal-oxide-semiconductor (MOS) capacitor is theoretically investigated with a series resistor. It is shown that compared to a conventional high-k dielectric MOS capacitor, a significant inversion charge-boost can be achieved by a FE MOS capacitor due to a steep transient subthreshold swing (SS) driven by the free charge-polarization mismatch. It is also shown that the observation of steep transient SS significantly depends on the viscosity coefficient under Landau's mean field theory, in general representing the average FE time response associated with domain nucleation and propagation. Therefore, this letter not only establishes a theoretical framework that describes the physical origin behind the inversion charge-boost in a FE MOS capacitor, but also shows that the key feature of depolarization effect on a FE MOS capacitor should be the inversion-charge boost, rather than the steep SS (e.g., sub-60mV/dec at room temperature), which cannot be experimentally observed as the measurement time is much longer than the FE response. Finally, we outlines the required material targets for the FE response in field-effect transistors to be applicable for next-generation high-speed and low-power digital switches.

Improved interfacial and electrical properties of HfLaON gate dielectric Ge MOS capacitor by NbON/Si dual passivation layer and fluorine incorporation

Ge metal-oxide-semiconductor (MOS) capacitor with HfLaON/(NbON/Si) stacked gate dielectric and fluorine-plasma treatment is fabricated, and its interfacial and electrical properties are compared with its counterparts without the Si passivation layer or the fluorine-plasma treatment. The experimental results show that the HfLaON/(NbON/Si) Ge MOS device treated by fluorine plasma exhibits excellent performance: low interface-state density (4.3 × 1011 cm−2 eV−1), small flatband voltage (0.22 V), good capacitance-voltage behavior, small frequency dispersion and low gate leakage current (4.18 × 10−5 A/cm2 at Vg = Vfb + 1 V). These should be attributed to the suppressed growth of unstable Ge oxides on the Ge surface during gate-dielectric annealing by the NbON/Si dual interlayer and fluorine incorporation, thus reducing the defective states at/near the NbSiON/Ge interface and improving the electrical properties of the device.

Photon-Induced Negative Capacitance in Metal Oxide Semiconductor Structures

Design and fabrication of photon-induced negative capacitance is presented. The capacitor is implemented using Silicon on Insulator Metal Oxide Semiconductor platform, where the gate dielectric is made of a nonferroelectric material. Operating at room temperature, when the device is illuminated, in depletion mode the total capacitance grows in magnitude to values larger than the geometrical capacitance. We believe this is caused by the trap states existing at the interface of dielectric and semiconductor layers, and present the supporting modeling results. Using our model, we investigate the role of the trap density and light intensity, as well as the device geometry such as gate-ground position and the thickness of the silicon layer. Our model shows the depletion capacitance can grow to values more than three times larger than the geometrical capacitance.

Performance analysis of SOI MOSFET with rectangular recessed channel

In this paper a two dimensional (2D) rectangular recessed channel–silicon on insulator metal oxide semiconductor field effect transistor (RRC-SOI MOSFET), using the concept of groove between source and drain regions, which is one of the channel engineering technique to suppress the short channel effect (SCE). This suppression is mainly due to corner potential barrier of the groove and the simulation is carried out by using ATLAS 2D device simulator. To have further improvement of SCE in RRC-SOI MOSFET, three more devices are designed by using dual material gate (DMG) and gate dielectric technique, which results in formation of devices i.e. DMRRC-SOI,MLSMRRC-SOI, MLDMRRC-SOI MOSFET. The effect of different structures of RRC-SOI on AC and RF parameters are investigated and the importance of these devices over RRC MOSFET regarding short channel effect is analyzed.

A two dimensional analytical modeling of surface potential in triple metal gate (TMG) fully-depleted Recessed-Source/Drain (Re-S/D) SOI MOSFET

In this paper, analytical modeling of surface potential is proposed for new Triple Metal Gate (TMG) fully depleted Recessed-Source/Dain Silicon On Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The metal with the highest work function is arranged near the source region and the lowest one near the drain. Since Recessed-Source/Drain SOI MOSFET has higher drain current as compared to conventional SOI MOSFET due to large source and drain region. The surface potential model developed by 2D Poisson's equation is verified by comparison to the simulation result of 2-dimensional ATLAS simulator. The model is compared with DMG and SMG devices and analysed for different device parameters. The ratio of metal gate length is varied to optimize the result.

Electrical properties of LaTiO high-k gate dielectric Ge MOS Capacitor and Ti content optimization

Ti is intentionally added into La2O3 to prepare LaTiO gate dielectric Ge metal-oxide-semiconductor (MOS) capacitor with both high k value and good interface quality. In order to examine the effects of Ti content on the electrical properties of the device, LaTiO films with different Ti/La2O3 ratios (10.6%, 18.4%, 25.7% and 31.5%) are deposited by reactively co-sputtering Ti and La2O3 targets. Capacitance-voltage curves, gate-leakage current properties and high-field stress characteristics of the devices are measured and analyzed. It is found that some electrical properties, such as interface-sate density, gate-leakage current, device reliability and k value, strongly depend on Ti content incorporated into La2O3. Ti incorporation can significantly increase the k value: the higher the Ti content, the larger the k value is. The relevant mechanism lies in the fact that higher Ti content leads to an increase of Ti-based oxide in the LaTi-based oxide, because Ti-based oxide has larger k value than La-based oxide. On the contrary, interface quality, gate-leakage current and device reliability deteriorate as Ti content increases because Ti-induced defects at and near the interface increase with Ti content increasing. Of the Ti/La2O3 ratios in the examined range, the largest Ti/La2O3 ratio is 31.5%, which results in the highest k value of 29.4, the largest gate-leakage current of 9.710-2 Acm-2 at Vg=1 V, the highest interface-sate density of 4.51012 eV-1cm-2 and the worst device reliability, while the La2O3 film without Ti incorporation exhibits the lowest k value of 11.7, the smallest gate-leakage current of 2.510-3 Acm-2 at Vg=1 V, the lowest interface-sate density of 3.31011 eV-1cm-2 and the best device reliability. As far as the trade-off among the electrical properties is concerned, 18.4% is the most suitable Ti/La2O3 ratio, which leads to a higher k value of 22.7, lower interface-sate density of 5.51011 eV-1cm-2, an acceptable gate-leakage current of 7.110-3 Acm-2 at Vg=1 V, and a better device reliability. In view of the fact mentioned above, excellent electrical properties could be obtained by setting Ti content to be an optimal value. Therefore, the optimization of Ti content is critical for LaTi-based oxide Ge MOS device preparation.

A novel Silicon on Insulator MOSFET with an embedded heat pass path and source side channel doping

In this paper we introduce a novel Silicon on Insulator Metal Oxide Semiconductor Field Effect Transistor (SOI MOSFET) with an embedded silicon heat pass path in the buried oxide (HPP-SOI). As this silicon path in the buried oxide conducts the generated heat in the active silicon channel from the shortest and most efficient path, self-heating effect improves while the fabrication process of this structure will remain without complexity. Moreover, the introduction of dopants in the source side of the channel leads to improvement in the leakage current, subthreshold slope, DIBL and threshold voltage roll-off in comparison with conventional SOI MOSFET (C-SOI). As proposed HPP-SOI structure shows these positive features, this structure can be considered as a serious candidate in nanoscale high temperature integrated applications.

High-k gate dielectric GaAs MOS device with LaON as interlayer and NH3-plasma surface pretreatment**Project supported by the National Natural Science Foundation of China (Grant Nos. 61176100 and 61274112).

High-k gate dielectric HfTiON GaAs metal-oxide–semiconductor (MOS) capacitors with LaON as interfacial passivation layer (IPL) and NH3- or N2-plasma surface pretreatment are fabricated, and their interfacial and electrical properties are investigated and compared with their counterparts that have neither LaON IPL nor surface treatment. It is found that good interface quality and excellent electrical properties can be achieved for a NH3-plasma pretreated GaAs MOS device with a stacked gate dielectric of HfTiON/LaON. These improvements should be ascribed to the fact that the NH3-plasma can provide H atoms and NH radicals that can effectively remove defective Ga/As oxides. In addition, LaON IPL can further block oxygen atoms from being in-diffused, and Ga and As atoms from being out-diffused from the substrate to the high-k dielectric. This greatly suppresses the formation of Ga/As native oxides and gives rise to an excellent high-k/GaAs interface.

Electrical Analysis of High Dielectric Constant Insulator and Metal Gate Metal Oxide Semiconductor Capacitors on Flexible Bulk Mono-Crystalline Silicon

We report on the electrical study of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors (MOSCAPs) on a flexible ultra-thin $(25~\mu{\rm m})$ silicon fabric which is peeled off using a CMOS compatible process from a standard bulk mono-crystalline silicon substrate. A lifetime projection is extracted using statistical analysis of the ramping voltage $({\rm V}_{\rm ramp})$ breakdown and time dependent dielectric breakdown data. The obtained flexible MOSCAPs operational voltages satisfying the 10 years lifetime benchmark are compared to those of the control MOSCAPs, which are not peeled off from the silicon wafer.

Mechanisms of temperature dependence of threshold voltage in high-k/metal gate transistors with different TiN thicknesses

The change in temperature coefficient of the threshold voltage (=dVth/dT) for poly-Si/TiN/high-k gate insulator metal–oxide–semiconductor field-effect transistors (MOSFETs) was systematically investigated with respect to various TiN thicknesses for both n- and p-channel MOSFETs. With increasing TiN thickness, dVth/dT shifts towards negative values for both n- and p-MOSFETs. A mechanism that changes dVth/dT, depending on TiN thickness is proposed. The main origins are the work function of TiN (ΦTiN) and its temperature coefficient (dΦTiN/dT). These are revealed to change when decreasing the thickness of the TiN layer, because the crystallinity of the TiN layer is degraded for thinner films, which was confirmed by ultraviolet photoelectron spectroscopy (UPS), transmission electron microscopy (TEM) and X-ray diffraction (XRD).

Study of electrical and micro-structural properties of high-κ gate dielectric stacks deposited using pulse laser deposition for MOS capacitor applications

The electrical properties of hafnium oxide (HfO2) gate dielectric as a metal–oxide–semiconductor (MOS) capacitor structure deposited using pulse laser deposition (PLD) technique at optimum substrate temperatures in an oxygen ambient gas are investigated. The film thickness and microstructure are examined using ellipsometer and atomic force microscope (AFM), respectively to see the effect of substrate temperatures on the device properties. The electrical J–V, C–V characteristics of the dielectric films are investigated employing Al–HfO2–Si MOS capacitor structure. The important parameters like leakage current density, flat-band voltage (Vfb) and oxide-charge density (Qox) for MOS capacitors are extracted and investigated for optimum substrate temperature. Further, electrical studies of these MOS capacitors have been carried out by incorporating La2O3 into HfO2 to fabricate HfO2/La2O3 dielectric stacks at an optimized substrate temperature of 800 °C using a PLD deposition technique under oxygen ambient. These Al–HfO2–La2O3–Si dielectric stacks MOS capacitor structure are found to possess better electrical properties than that of HfO2 based MOS capacitors using the PLD deposition technique.

A Theoretical Study on Electron Tunneling Current in Isotropic High-κ Dielectric Stack-Based MOS Capacitors with Charge Trapping

Electron tunneling current in an isotropic metal-oxide-semiconductor (MOS) capacitor with a high-κ dielectric stack has been studied by considering the effect of charge trapping. The transmittance was analytically calculated by employing an Airy-wavefunction approach and including a coupling term between the transverse and longitudinal kinetic energies which is represented by an electron phase velocity in the gate. The transmittance was then applied to obtain tunneling currents in isotropic n+poly-Si/HfSiOxN/trap/SiO2/Si (100) MOS capacitors for different electron gate phase velocities and trap depths and widths. The calculated results show that the transmittance and tunneling current increase as the electron gate velocity decreases. In addition, the increase in the trap depth and width enhances the tunneling current.

Improved interface properties of an HfO2 gate dielectric GaAs MOS device by using SiNx as an interfacial passivation layer

A GaAs metal-oxide-semiconductor (MOS) capacitor with HfO2 as gate dielectric and silicon nitride (SiNx) as the interlayer (IL) is fabricated. Experimental results show that the sample with the SiNx IL has an improved capacitance—voltage characteristic, lower leakage current density (0.785 × 10−6 A/cm2 at Vfb + 1 V) and lower interface-state density (2.9 × 1012 eV−1 cm−2) compared with other samples with N2− or NH3—plasma pretreatment. The influences of post-deposition annealing temperature on electrical properties are also investigated for the samples with SiNx IL. The sample annealed at 600°C exhibits better electrical properties than that annealed at 500°C, which is attributed to the suppression of native oxides, as confirmed by XPS analyses.

Strain Engineering of Plasma Dispersion Effect for SiGe Optical Modulators

The plasma dispersion effect and free-carrier absorption in strained SiGe are analyzed using the six-band k· <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</i> method and the Drude model. Since the hole conductivity mass of SiGe is decreased by applying compressive strain, enhancement of the plasma dispersion effect, and free-carrier absorption in strained SiGe is expected. We predict that Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> coherently grown on Si will exhibit three times higher plasma dispersion and four times higher free-carrier absorption than Si. The modulation characteristics of SiGe quantum well metal-oxide-semiconductor (MOS) optical modulators are also analyzed by technology computer-aided design simulation and finite-difference optical mode analysis. An extremely small V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">π</sub> L of 0.033 V-cm is predicted in the case of a compressively strained Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> quantum well in conjunction with a high-k gate dielectric MOS structure. The enhancement of free-carrier absorption in the SiGe high-k MOS modulator also makes in-line intensity modulation feasible and an intensity modulation efficiency of 9 dB/mm/V is predicted.

A new nanoscale and high temperature field effect transistor: Bi level FinFET

In this paper, we propose a new Bi Level Fin Field Effect Transistor (BL-FinFET) where the fin regions consist of Bi level. The novel features of the BL-FinFET are simulated and compared with a Conventional FinFET (C-FinFET). The three-dimensional and two-carrier device simulation demonstrate that the application of Bi level to the FinFET structure results in an ideal threshold voltage roll-off, reduced DIBL, excellent behavior in voltage gain at high temperatures and the gate capacitance improvement when compared with the C-FinFET. Also, this paper illustrates the benefits of the high performance BL-FinFET device over the conventional one and expands the application of Silicon on Insulator Metal Oxide Semiconductor Field Effect Transistors (SOI MOSFETs) to high temperature.

Nitrogen dependence of band alignment and electrical properties of HfTiON gate dielectrics metal-oxide-semiconductor capacitor

The effect of nitrogen incorporation on the band alignment and electrical properties of HfTiO gate dielectric complementary metal-oxide-semiconductor (MOS) capacitors has been investigated by spectroscopy ellipsometry, x-ray photoelectron spectroscopy, and electrical measurements. Reduction in optical band gap and band offsets has been detected. However, improved electrical properties have been achieved from HfTiON gate dielectric MOS capacitors attributed to the nitrogen-induced reduction in oxygen-related traps and the improved interface quality. Although there is a nitrogen-induced reduction in band gap and band offset, the sufficient barrier heights still makes HfTiON a promising high-k gate dielectric candidate for proposed near-future complementary metal-oxide-semiconductor applications.