Insulator Metal Oxide Semiconductor Field Research Articles

Impact of Structural Aspect, Metal Gate and Channel Material on UTB-SOI-MOSFET

Ultra Thin Body Silicon on Insulator Metal Oxide Semiconductor Field Effect Transistors (UTB-SOI-MOSFETs) provide better immunity to Short Channel Effects (SCEs). But the behaviour changes at miniaturization and still the many unexplored effects need to be analysied. Here in this paper, Drain Induced Barrier Lowering (DIBL) and sub-threshold Slope (SS) variation of a n-channel UTB-SOI-MOSFET have been analyzed by changing the device structural aspects like gate length (LG), BOX thickness (tBOX) and Silicon film thickness (tSi). Also, the effect of intrinsic parameters as metal gate work function and channel material variation on DIBL and sub-threshold Slope (SS) variation has been analyzed.

Performance analysis of SOI MOSFET with rectangular recessed channel

In this paper a two dimensional (2D) rectangular recessed channel–silicon on insulator metal oxide semiconductor field effect transistor (RRC-SOI MOSFET), using the concept of groove between source and drain regions, which is one of the channel engineering technique to suppress the short channel effect (SCE). This suppression is mainly due to corner potential barrier of the groove and the simulation is carried out by using ATLAS 2D device simulator. To have further improvement of SCE in RRC-SOI MOSFET, three more devices are designed by using dual material gate (DMG) and gate dielectric technique, which results in formation of devices i.e. DMRRC-SOI,MLSMRRC-SOI, MLDMRRC-SOI MOSFET. The effect of different structures of RRC-SOI on AC and RF parameters are investigated and the importance of these devices over RRC MOSFET regarding short channel effect is analyzed.

A novel Silicon on Insulator MOSFET with an embedded heat pass path and source side channel doping

In this paper we introduce a novel Silicon on Insulator Metal Oxide Semiconductor Field Effect Transistor (SOI MOSFET) with an embedded silicon heat pass path in the buried oxide (HPP-SOI). As this silicon path in the buried oxide conducts the generated heat in the active silicon channel from the shortest and most efficient path, self-heating effect improves while the fabrication process of this structure will remain without complexity. Moreover, the introduction of dopants in the source side of the channel leads to improvement in the leakage current, subthreshold slope, DIBL and threshold voltage roll-off in comparison with conventional SOI MOSFET (C-SOI). As proposed HPP-SOI structure shows these positive features, this structure can be considered as a serious candidate in nanoscale high temperature integrated applications.

A new nanoscale and high temperature field effect transistor: Bi level FinFET

In this paper, we propose a new Bi Level Fin Field Effect Transistor (BL-FinFET) where the fin regions consist of Bi level. The novel features of the BL-FinFET are simulated and compared with a Conventional FinFET (C-FinFET). The three-dimensional and two-carrier device simulation demonstrate that the application of Bi level to the FinFET structure results in an ideal threshold voltage roll-off, reduced DIBL, excellent behavior in voltage gain at high temperatures and the gate capacitance improvement when compared with the C-FinFET. Also, this paper illustrates the benefits of the high performance BL-FinFET device over the conventional one and expands the application of Silicon on Insulator Metal Oxide Semiconductor Field Effect Transistors (SOI MOSFETs) to high temperature.

Simulation of asymmetric doped high performance silicon on insulator metal oxide semiconductor field effect transistors for very large scale integrated complementary metal oxide semiconductor technologies

Asymmetric halo and extension implantations are examined by simulation for their usability in 45 and 32 nm technology high performance silicon on insulator metal oxide semiconductor field effect transistors (SOI-MOSFETs). Tilted halo and extension implantations from the source side show higher saturation currents and lower drain overlap and junction capacitances, which improve the intrinsic MOSFET power delay product. Furthermore the asymmetric doping profile leads to an inverter chain speed benefit. The stronger short channel effect, present in these devices, can be reduced by a low dose drain side halo implantation simultaneously maintaining a transistor performance improvement from asymmetric doping. This optimized transistor design is successfully transferred from the 45 into the 32 nm technology.

Detailed simulation study of embedded SiGe and Si:C source/drain stressors in nanoscaled silicon on insulator metal oxide semiconductor field effect transistors

Strained silicon techniques have become an indispensable technology feature, enabling the momentum of semiconductor scaling. Embedded silicon-germanium (eSiGe) is already widely adopted in the industry and delivers outstanding p-metal oxide semiconductor field effect transistor (MOSFET) performance improvements. The counterpart for n-MOSFET is embedded silicon-carbon (eSi:C). However, n-MOSFET performance improvement is much more difficult to achieve with eSi:C due to the challenging process integration. In this study, detailed TCAD simulations are employed to compare the efficiency of eSiGe and eSi:C stressors and to estimate their potential for performance enhancements in future nanoscaled devices with gate lengths down to 20nm. It is found that eSiGe as a stressor is superior to eSi:C in deeply scaled and highly strained devices due to its easier process integration, reduced parasitic resistance, and nonlinear effects in the silicon band structure, favoring hole mobility enhancement at high strain levels.

Scalable gate first process for silicon on insulator metal oxide semiconductor field effect transistors with epitaxial high-k dielectrics

A “gate first” silicon on insulator (SOI) complementary metal oxide semiconductor process technology for direct evaluation of epitaxial gate dielectrics is described, where the gate stack is fabricated prior to any lithography or etching step. This sequence provides perfect silicon surfaces required for epitaxial growth. The inverted process flow with silicon dioxide (SiO2)/polysilicon gate stacks is demonstrated for gate lengths from 10μm down to 40nm on a fully depleted 25nm thin SOI film. The interface qualities at the front and back gates are investigated and compared to conventionally processed SOI devices. Furthermore, the subthreshold behavior is studied and the scalability of the gate first approach is proven by fully functional sub-100nm transistors. Finally, a fully functional gate first metal oxide semiconductor field effect transistor with the epitaxialhigh-k gate dielectric gadolinium oxide (Gd2O3) and titanium nitride (TiN) gate electrode is presented.

Novel Silicon On Insulator Metal Oxide Semiconductor Field Effect Transistors with Buried Back Gate

One of the most promising ways of realizing metal oxide semiconductor field effect transistors (MOSFETs) with high speed and ultralow power consumption is by varying the threshold voltage of fully depleted silicon on insulator (FD-SOI) MOSFETs by changing back gate bias. We have studied FD-SOI MOSFETs with buried back gate by experiment and simulation in order to realize both high-performance and low-voltage ULSIs. It was confirmed that the back gate is very effective not only for increasing the ON current in the active mode but also for decreasing the cut-off current in the standby mode by controlling the threshold voltage.

Analyses of the Radiation-Caused Characteristics Change in SOI MOSFETs Using Field Shield Isolation

Reliability against radiation is an important issue in silicon on insulator metal oxide semiconductor field effect transistors (SOI MOSFETs) used in satellites and nuclear power plants and so forth which are severely exposed to radiation. Radiation-caused characteristic change related to the isolation-edge in an irradiated environment was analyzed on SOI MOSFETs. Moreover short channel effects for an irradiated environment were investigated by simulations. It was revealed that the leakage current which was observed in local oxidation of silicon (LOCOS) isolated SOI MOSFETs was successfully suppressed by using field shield isolation. Simulated potential indicated that the potential rise at the LOCOS edge can not be seen in the case of field shield isolation edge which does not have physical isolation. Also it was found that the threshold voltage shift caused by radiation in short channel regime is severer than that in long channel regime. In transistors with a channel length of 0.18 µm, a potential rise of the body region by radiation-induced trapped holes can be seen in comparison with that of 1.0 µm. As a result, we must consider these effects for designing deep submicron devices used in an irradiated environment.

An Investigation on the Short Channel Effect for 0.1 µm Fully Depleted SOIMOSFET Using Equivalent One Dimensional Model

An analytical model for the short channel effect for the silicon on insulator metal oxide semiconductor field effect transistor (SOIMOSFET) is proposed. The two dimensional potential problem is reduced to a one dimensional problem, using a virtual electrode which is equivalent to the drain and the source electrodes. The behavior for the short channel effect is also discussed using this model.

Current-Voltage Characteristics of Silicon on Insulator Metal Oxide Semiconductor Field Effect Transistors in Ballistic Mode

Current-voltage characteristics of ultrathin silicon on insulator n-type MOSFETs (metal oxide semiconductor field effect transistors) operating in ballistic transport mode are given. They are derived with the similar guiding principle as that used in quantum point contact. The obtained result is independent of channel length, and is expressed with elementary parameters without depending on ambiguous carrier mobility. They show triode and pentode operational modes similarly to the normal MOSFET. When inversion carriers are degenerate, saturation current is independent of temperature and is proportional to the carrier density to the power of 1.5.