Insulator Metal Oxide Semiconductor Field Effect Transistor Research Articles

A critical evaluation based on Lattice Boltzmann method of nanoscale thermal behavior inside MOSFET and SOI-MOSFET

In recent years, the world has witnessed a huge technological revolution in terms of manufacturing electronic devices and reducing their size, which has reached nanoscale. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is one of these devices. However, with its downsizing, it affects the efficiency of its associated devices due to the generated heat. In this paper, two-dimensional heat transfer inside a Silicon on Insulator (SOI) MOSFET and traditional MOS transistor is investigated using the Lattice Boltzmann Method (LBM) . It was found that the temperature reaches 340 K and 332 K for SOI-MOSFET and MOSFET at a Knudsen number (Kn=Λ/Lc) of 10, respectively, while the heat flux reaches 21.5 × 1011 W/m2 for SOI transistor and 18.7 × 1011 W/m2for MOS device. The insulating layer (SiO2)in the SOI transistor restrains heat release in the channel region. So, the conventional MOSFET at Kn =10 is thermally more stable, compared to SOI-MOSFET.

Study of robin condition influence on phonon nano-heat conduction using meso-scale method in MOSFET and SOI-MOSFET devices

Metal oxide semiconductor field effect transistor (MOSFET) is a major element of electronic device circuits due to its ability to control the electrical signal. On the other hand, the size of this device became smaller, reached nanoscale. Several macroscopic theoretical studies have been documented on the importance of the thermal behavior in these nano-transistors. This paper provides a developed approach to study the nano-heat conduction coupled with Robin boundary condition and temperature jump boundary condition in MOSFET and Silicon on Insulator (SOI) MOSFET using the mesoscopic Boltzmann transport equation. The results indicated that there was a positive relationship between the increasing of inverse thermal resistance (Rth−1) and the reducing temperature in the source/drain for both devices while the maximal temperature at the interface semiconductor-wall decreases slightly for Rth−1=1010 W/m²∙K at t= 30 ps reaching 331.7 K for MOSFET and 338.5 K for SOI-MOSFET. The effect of heat generated in the active channel is more profound than the effect of Robin condition for Rth−1=107, 108, and 109 W/m²∙K at t = 10 ps. The most obvious findings to emerge from this study is that Robin boundary condition has a slight impact on heat along the channel region at a short time. In addition, this study identified the effect of layer oxide, which stores the heat between the source and the drain.

Influence of Structural Parameters on the Behavior of an Asymmetric Linearly Graded Workfunction Trapezoidal Gate SOI MOSFET

This paper presents a dual metal trapezoidal recessed channel metal oxide semiconductor field effect transistor (MOSFET) embedded with asymmetric stack gate with linearly graded metal work-function technique to improve the carrier transport efficiency and device switching performance. The analytical model for the proposed asymmetric-linearly graded trapezoidal gate (ASY–LGTG) silicon on insulator (SOI) MOSFET has been developed considering parabolic approximation of 2-D Poisson’s equation. The threshold voltage of the device is extracted using minimum surface potential. The simulation work has been carried out using a Silvaco TCAD tool to validate the results of the analytical model. This grooved structure exhibits the corner effect, which plays a dynamic role in the improvement of the device performance. However, the impact of the corner effect can be controlled by the groove corner angle and doping concentration. We have also investigated the impact of different structural parameters such as negative junction depth (NJD), corner angle, substrate doping and stack gate features (upper oxide permittivity and oxide thickness ratio) on the performance of minimum surface potential, sub-threshold slope (SS), drain induced barrier lowering (DIBL), threshold voltage and device switching characteristics.

Development of Tri‐Layered s‐Si/s‐SiGe/s‐Si Channel Heterostructure‐on‐Insulator MOSFET for Enhanced Drive Current

Incubation of strain technology in the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) arena by developing heterostructure layers combined of Si and SiGe layers within the channel is employed widely. Development of a fully depleted novel device featuring a distinguished tri‐layer heterostructure channel consisting of mobility enriched double strained Si (s‐Si) layers sandwiching strained SiGe (s‐SiGe) in between has been the crux of this paper. The channel with s‐Si/s‐SiGe/s‐Si significantly enhances electron mobility in comparison to conventional device of s‐Si on relaxed SiGe channel, leading to improved device performance without implementing additional scaling. The tri‐layered channel and the conventional device are compared and eloquent drain current enhancement of 49% attained with minimal value of threshold voltage roll‐off with increased strain infusion within the channel region, which augments electron mobility in the s‐Si layers. Augmented maximum transconductance for sub‐50 nm channel length due to velocity overshoot enhancement of 119% in comparison to conventional device acquired lead to ≈25% decrease in threshold voltage by band structure lowering with the instigation of the strain technology in the short channel device attained. Hence, with higher carrier mobility and improved drive current double strained Si heterostructure on insulator (HOI) MOSFET device is designed and developed.

Static power characteristics of selective buried oxide CMOS devices

AbstractSelective buried oxide (SELBOX) Metal‐Oxide‐Semiconductor Field‐Effect Transistor (MOSFET) structure can be used to reduce the kink effect and self‐heating problems associated with the silicon on insulator (SOI) MOSFET devices while maintaining the advantages of bulk MOSFET. In this paper, static power dissipation of SELBOX structure is investigated and compared with SOI and bulk structures. Various MOSFET structures are simulated and evaluated in terms of their static power dissipation. Only results from 90‐nm Complementary Metal Oxide Semiconductor (CMOS) technology devices are included in this paper. Simulation results using the Silvaco TCAD show that static power dissipation in SELBOX CMOS is similar to that of SOI devices but lower than that of bulk CMOS. Hence, SELBOX structure is found to produce relatively low‐static power dissipation while maintaining high operating speed and reducing self‐heating and kink effect. A mathematical model to describe the static power dissipation in the subthreshold region is also included. Statistical analysis show that the model and fabrication simulation results agree with P < .05 and correlation coefficient of 0.95.

Fully subthreshold current-based characterization of interface traps and surface potential in III–V-on-insulator MOSFETs

We report characterization of the interface trap distribution (Dit(E)) over the bandgap in III–V metal–oxide–semiconductor field-effect transistors (MOSFETs) on insulator. Based only on the experimental subthreshold current data and differential coupling factor, we simultaneously obtained Dit(E) and a nonlinear mapping of the gate bias (VGS) to the trap level (Et) via the effective surface potential (ψS,eff). The proposed technique allows direct extraction of the interface traps at the In0.53Ga0.47As-on insulator (-OI) MOSFETs only from the experimental subthreshold current data. Applying the technique to the In0.53Ga0.47As channel III–V-OI MOSFETs with the gate width/length W/L=100/50, 100/25, and 100/10μm/μm, we obtained Dit(E)≅1011–1012eV−1cm−2 over the bandgap without the dimension dependence.

A SiGe on insulator MOSFET to improve the electrical performances: Amended channel band energy

In this paper, a novel nanoscale SiGe-on-insulator (SGOI) metal oxide-semiconductor field-effect transistor (MOSFET) is presented by amended channel band energy. The main idea in this work is to improve the electrical parameters by altering the channel band energy. Vertical graded Ge composition profile is utilized in the channel. Therefore, the proposed structure is named VGC-SGOI. The electrical performances of the VGC-SGOI are analyzed via a 2-D numerical simulation and the results are compared with characteristics of a uniform germanium composition SGOI (UC-SGOI) structure. Due to increment in the potential barriers and the slope of conduction/valence band by employing the vertical graded Ge composition profile, the VGC-SGOI has lower leakage current and higher saturation drain current in comparison with the UC-SGOI. Furthermore, the proposed structure suppresses short channel effects (SCEs) and drain induced barrier lowering (DIBL). Consequently, the VGC-SGOI has a superior candidate for high performance devices.

Mechanisms of temperature dependence of threshold voltage in high-k/metal gate transistors with different TiN thicknesses

The change in temperature coefficient of the threshold voltage (=dVth/dT) for poly-Si/TiN/high-k gate insulator metal–oxide–semiconductor field-effect transistors (MOSFETs) was systematically investigated with respect to various TiN thicknesses for both n- and p-channel MOSFETs. With increasing TiN thickness, dVth/dT shifts towards negative values for both n- and p-MOSFETs. A mechanism that changes dVth/dT, depending on TiN thickness is proposed. The main origins are the work function of TiN (ΦTiN) and its temperature coefficient (dΦTiN/dT). These are revealed to change when decreasing the thickness of the TiN layer, because the crystallinity of the TiN layer is degraded for thinner films, which was confirmed by ultraviolet photoelectron spectroscopy (UPS), transmission electron microscopy (TEM) and X-ray diffraction (XRD).

Microscale thermal conduction based on Cattaneo-Vernotte model in silicon on insulator and Double Gate MOSFETs

We study heat transfer process in a 10 nm Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) based on Silicon on Insulator (SOI) and Double Gate (DG). In this numerical investigation, we used the Cattaneo-Vernotte (CV) model coupled with a new boundary condition, usually termed as second order temperature jump. We solved the problem in a two-dimensional configuration using the finite element method. By taking into account the lag effect, our new model avoids the infinite heat propagation speed adopted by the Fourier's law. The heat generation is assumed to be uniform in the active zone. It was found that the CV model coupled with the second order temperature jump is able to predict the heat transfer obtained from Boltzmann Transport equation (BTE) and Ballistic Diffusive equation (BDE). In addition, the DG-MOSFET is revealed to be more thermally efficient compared with classical and SOI-MOSFETs.

SiGe on Insulator MOSFET Integrated with Schottky Source/Drain and HfO[sub 2]∕TaN Gate Stack

We demonstrate high Ge percentage thin silicon germanium on insulator (SGOI) p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) using Ni-germanosilicide Schottky source/drain (S/D) and HfO 2 /TaN gate stack integrated with conventional self-aligned top gate process. Unlike high-temperature S/D activation needed for conventional transistor, low Ni-germanosilicide S/D formation temperature contributes to the excellent capacitance-voltage characteristic and low gate leakage current. SGOI structure suppresses the junction leakage problem, resulting in good agreement between the source current and drain current. In addition, extracted peak hole mobility is comparable to that of conventional bulk Ge p-MOSFET with HfO 2 /TaN gate stack.

Evaluations of Scaling Properties for Ge on Insulator MOSFETs in Nano-Scale

Germanium metal-oxide-semiconductor field-effect transistors (MOSFETs) have attracted tremendous attention due to the high carrier mobility especially in the low-field. Compared to Si, in bulk germanium the velocity would saturate at a lower field with a lower saturation velocity. Thus the scaling behavior of germanium MOSFET with gate length in nano-scale is very important. In this work, characteristics of both n- and p-channel germanium on Insulator (GOI) MOSFETs with channel length (Lch) ranging from 20 nm to 130 nm are simulated by 2D self-consistent full-band Monte Carlo device simulator to investigate the scaling properties. The results indicate that both for n and p channel GOI MOSFETs have favorable scaling properties in nano-scale due to the non-stationary transport near source side especially for p channel device. But the surface roughness scattering is a critical issue that might suppress the non-stationary transport. Short channel effect (SCE) is serious in GOI devices and much thinner Germanium layer have to use to optimize the performance.

Temperature Dependence of Off-Current in Bulk and Fully Depleted SOI MOSFETs

Re-examinations of the temperature dependence of off-current (Ioff) in metal oxide semiconductor field-effect transistors (MOSFETs) have been carried out, from 0.25 µm to 65 nm technology nodes comparing bulk MOSFETs to fully depleted silicon on insulator (FD SOI) MOSFETs. Analytical calculations and two-dimensional (2D) device simulations are performed, and the ratio of Ioff at a high temperature to that at room temperature has been focused on for discussion. The temperature dependence of Ioff consists of two components: subthreshold factor component (S component) and threshold voltage component (Vth component). It is found that the Vth component determines the relative merits of bulk and FD SOI MOSFETs, and originates from the difference in the temperature dependence of Vth. It is also found from the simulation that, although the advantage of FD SOI MOSFETs remains when the short-channel effect can be neglected, it diminishes when the short-channel effect is dominant as the technology node advances.

Novel Silicon On Insulator Metal Oxide Semiconductor Field Effect Transistors with Buried Back Gate

One of the most promising ways of realizing metal oxide semiconductor field effect transistors (MOSFETs) with high speed and ultralow power consumption is by varying the threshold voltage of fully depleted silicon on insulator (FD-SOI) MOSFETs by changing back gate bias. We have studied FD-SOI MOSFETs with buried back gate by experiment and simulation in order to realize both high-performance and low-voltage ULSIs. It was confirmed that the back gate is very effective not only for increasing the ON current in the active mode but also for decreasing the cut-off current in the standby mode by controlling the threshold voltage.

Comparison Between High- and Low-Dose Separation by Implanted Oxygen MOS Transistors for Low-Power Radio-Frequency Applications

In this work, metal-oxide-semiconductor (MOS) field effect transistors (MOSFET) fabricated on low- and high-dose separation by implanted oxygen (SIMOX) substrates are compared in terms of RF performance. Combining S-parameter measurements with an accurate extraction method of small-signal model parameters enables us to investigate the RF performances of these two technologies and to evaluate the impact of the self-heating effect on silicon on insulator (SOI) MOSFET performances in this range. The cut-off frequency behavior of these two SOI MOSFET types is therefore analysed. In addition, using an analytical model, the influence of the buried oxide thickness on the coplanar transmission lines is investigated. All these results show the potentiality of the low-dose SIMOX technology for low-power radio-frequency applications.

New Measurement Technique for Sub-Bandgap Impact Ionization Current by Transient Characteristics of Partially Depleted SOI MOSFETs

We have developed a novel, sensitive measurement technique for the sub-bandgap impact ionization current in scaled metal-oxide-semiconductor field effect transistors (MOSFETs). In this technique, partially depleted silicon on insulator MOSFETs is utilized where the floating body potential is gradually charged by the impact ionization current. The transient increase of the body potential causes a decrease in the threshold voltage due to the body effect, resulting in a transient increase in the drain current. The impact ionization current is derived from the transient increase in the body potential. The derived impact ionization current is in good agreement with the direct current measurement. Furthermore, the new measurement technique is very sensitive even in the sub-bandgap region and measurements of less than 50 fA are demonstrated.

Ballistic metal-oxide-semiconductor field effect transistor

Experiments on ultra-small metal-oxide-semiconductor field effect transistors (MOSFETs) less than 100 nm have been widely reported recently. The frequency of carrier scattering events in these ultra-small devices is diminished, so that further suppression of carrier scattering may bring these devices close to the regime of ballistic transport. Carrier scattering is suppressed by constructing their channel regions with intrinsic Si and also by low temperature operation. This article proposes the ballistic transport of carriers in MOSFETs, and presents the current-voltage characteristics of the ballistic n-channel MOSFET. The current is expressed with the elementary parameters without depending on the carrier mobility. It is independent of the channel length and is proportional to the channel width. The current value saturates as the drain voltage is increased and the triode and the pentode operation are specified as in the conventional MOSFET. Similar current-voltage characteristics in the ballistic transport regime are also investigated for the p-channel MOSFET, the dual gate ultra-thin silicon on insulator MOSFET, and the high electron mobility transistor device. The obtained current gives the maximum current limitation of each field effect transistor geometry. The current control mechanism of ballistic MOSFETs is discussed. The current value is governed by the product of the carrier density near the source edge in the channel, and the velocity with which carriers are injected from the source into the channel. Influence of optical phonon emission to the transport is discussed. It is suggested that if the device is operated with relatively low carrier density at low temperatures, and if the scattering processes other than the optical phonon emission are suppressed so as to attain the ballistic transport, the optical phonon emission is also suppressed and ballistic transport is sustained. A convenient figure of merit to show the ballisticity of carrier transport in an experimental MOSFET is proposed. Its value is estimated for some examples of the recent ultra-small MOSFET experiment. The proposed current voltage characteristics are evaluated for a dual gate silicon on insulator MOSFET geometry. The result is compared with the recently reported elaborate Monte Carlo simulation with satisfactory agreement.