Gate Dielectric Research Articles

Neuro‐Actuating Photonic Skin Enabled by Ion‐Gel Transistor with Thermo‐Adaptive Block Copolymer

AbstractDespite significant progress in developing artificial synapses to emulate the human nervous system for bio‐signal transmission, synapses with thermo‐adaptive coloration and soft actuators driven by temperature change have seldom been reported. Herein, a photonic neuro‐actuating synaptic skin is presented enabling thermoresponsive synaptic signal transmission, color variation, and actuation. First, a thermoresponsive display synapse is developed based on a 3‐terminal ion‐gel transistor with a poly (3,4‐ethylene dioxythiophene):poly (styrene sulfonate) (PEDOT:PSS) semiconducting channel mixed with 2D titanium carbide (Ti3C2Tx) MXene and a thermo‐adaptive 1D block copolymer (BCP) photonic crystal (PC) gate insulator. Temperature‐dependent synaptic behavior is successfully observed in the ion‐gel transistor with the corresponding structural colors, leading to a thermo‐adaptive display synapse. The 3 × 3 arrays of thermo‐adaptive display synapses with Joule heaters show that each pixel is controlled by the thermoresponsive structural color and synaptic output. The synaptic output current from the MXene ion‐gel transistor can be converted and amplified to a voltage signal, which powers a soft actuator connected to the ion‐gel display synapse and triggers temperature‐dependent actuation related to the thermoresponsive synaptic performance. This study showcases a thermo‐adaptive photonic neuro‐actuating artificial skin that emulates muscle‐combined neuronal human skin with visualization capability.

Opto‐Electrical Decoupled Phototransistor for Starlight Detection

AbstractHighly sensitive shortwave infrared (SWIR) detectors are essential for detecting weak radiation (typically below 10−8 W·Sr−1·cm−2·µm−1) with high‐end passive image sensors. However, mainstream SWIR detection based on epitaxial photodiodes cannot effectively detect ultraweak infrared radiation due to the lack of inherent gain. Here, we develop a heterojunction‐gated field‐effect transistor (HGFET) consisting of a colloidal quantum dot (CQD)‐based p‐i‐n heterojunction and a carbon nanotube (CNT) field‐effect transistor, which achieves a high inherent gain based on an opto‐electric decoupling mechanism for suppressing noise. The stacked heterojunction absorbs infrared radiation and separates electron–hole pairs. Then, the generated photovoltage tunes the drain current of the CNT FET through an Y2O3 gate insulator. As a result, the HGFET significantly detects and amplifies SWIR signals with a high inherent gain while minimally amplifying noise, leading to a recorded specific detectivity above 1014 Jones at 1300 nm and a recorded maximum gain‐bandwidth product of 69.2 THz. Direct comparative testing indicates that the HGFET can detect weak infrared radiation at 0.46 nW cm−2 levels; thus, compared to commercial and reported SWIR detectors, this detector is much more sensitive and enables starlight detection or vision. As the fabrication process is very compatible with CMOS readout integrated circuits, the HGFET is a promising SWIR detector for realizing passive night vision imaging sensors with high resolutions that are high‐end, highly sensitive, and inexpensive.

High Memory Window, Dual‐Gate Amorphous InGaZnO Thin‐Film Transistor with Ferroelectric Gate Insulator

Ferroelectric (FE) hafnium zirconium oxide (HZO) thin‐film transistors (TFTs) are of increasing interest for next‐generation memory and computing applications. However, these devices face challenges in achieving a substantial memory window (MW). This report presents amorphous InGaZnO (a‐IGZO) ferroelectric–dielectric (FD), dual‐gate thin‐film transistors (DG‐TFTs) with FE‐HZO as a bottom gate insulator (GI) and SiO2 as a top GI. The ferroelectricity in HZO is confirmed through the grazing incidence X‐ray diffraction (GI‐XRD), capacitance, and polarization measurements. The FD‐DG TFT can increase the MW by tuning the threshold voltage (VTH) due to electrostatic coupling between the top gate (TG) and bottom gate (BG). The increase of MW at the TG driving is related to the coupling factor which is equal to the ratio of the equivalent capacitance of top to bottom gated transistors. During the bottom sweep, the FD‐DG‐TFT demonstrates an anticlockwise hysteresis with a MW of 4.98 V, a high ION/IOFF ratio of ≈106, and a steep subthreshold swing (SS) of 90 mV dec−1. On the contrary, MW of 12 V and SS of 140 mV dec−1 are observed for the top sweep operation. A thinner ferroelectric GI at BG TFT induces sufficient electrostatic coupling to cause a large VTH shift at TG driving, resulting in a boosted MW.

A Single-Crystal Antimony Trioxide Dielectric for 2D Field-Effect Transistors.

The remarkable potential of two-dimensional (2D) materials in sustaining Moore's law has sparked a research frenzy. Extensive efforts have been made in the research of utilizing 2D semiconductors as channel materials in field-effect transistors. However, the next generation of integrated devices requires the integration of gate dielectrics with wider bandgaps and higher dielectric constants. Here, insulating α-Sb2O3 single-crystal nanosheets are synthesized by one-step chemical vapor deposition method. Importantly, the α-Sb2O3 single-crystal dielectric exhibits a high dielectric constant of 11.8 and a wide bandgap of 3.78 eV. Besides, the atomically smooth interface between α-Sb2O3 and MoS2 enables the fabrication of dual-gated field-effect transistors with the top gate dielectric of α-Sb2O3 nanosheets. The field-effect transistors exhibit a switching ratio of exceeding 108, which achieves the manipulation of field-effect transistors by using 2D dielectric materials. These results hold significant implications for optimizing the performances of 2D devices and innovating microelectronics.

Device to circuit level implementation of JL-NSFET for DC/analog/RF applications at sub-5nm technology node: design optimization and temperature analysis

Abstract This manuscript introduces, for the first time, a novel approach that incorporates a comprehensive analysis of sheet variations (1–5) and every individual sheet wise temperature variation, and as well as an investigation of various GS high-k gate dielectrics in Junction-less (JL) Nanosheet FET (JL-NSFET). The study starting from device level (Digital/Analog/Radio Frequency) to circuit (CMOS Inverter and ring oscillator) as a whole package is investigated through well calibrated TCAD simulation and the results portrayed. NSFETs are the ultimate choice for integrated circuits (ICs) at sub-5 nm technology node. The notion of this paper is to design and optimization of NSFET with GS high-k gate dielectrics (Al2O3, HfO2, ZrO2 and TiO2) Initially. The switching/analog and RF metric revels that HfO2 is superior in terms SS, switching applications and more compactable with CMOS process. Further, adding number of sheets and temperature variation has been done later. As number of sheets increases, the effective channel width increases, electric field distribution takes place evenly and enhanced gate control owing to improved I O N , I O N / I O F F r a t i o , SS and DIBL. However, increasing the number of vertical channel layers (sheets) more than 2 results into diminished analog/RF performance of JL-NSFET owing to increased parasitic capacitances. Further, the impact of temperature variations (250 K to 450 K) studied for different sheet variations (1 to 5) and noticed that analog/RF such as gm, gds, fT, TFP and GTFP are enhanced by 40.82%, 28.76%, 40.69%, 64.62% and 70.59%, respectively at lower temperature (250 K) when compared to high temperature (450 K). These enhancements make the device is ideal for applications in cryogenic computing systems, satellites, deep space probes, and other aerospace technologies. Furthermore, as the circuit level implementation CMOS inverter and 5-stage ring oscillator (RO) are examined for different sheets and observed as sheets increase delay and EDP increases. For a CMOS inverter the NMH (0.295 V) and NML (0.280 V) are better at 2 sheets with a highest gain of 9.38 V/V. Hence, it is advised to use two or three sheets-based JL-NSFETs for high-performance and lower-power analog/RF applications.

Temperature Dependent Growth of Ytterbium Oxide as Gate Dielectric on Silicon Substrate Via Combination of Nitrogen and Oxygen Ambient

The ongoing trend towards downsizing silicon (Si)-based metal-oxide semiconductor (MOS) devices has led to constraints on the silicon dioxide (SiO2) gate dielectric due to increased leakage current through the thin SiO2. In this study, ytterbium oxide (Yb2O3) as a high dielectric constant (k) gate oxide material was deposited on a Si substrate and subjected to annealing at different temperatures ranging from 400 to 1000oC in a nitrogen-oxygen-nitrogen ambient atmosphere. The successful formation of Yb2O3 was verified using X-ray diffraction (XRD), Fourier transform infrared (FTIR), and ultraviolet-visible (UV-VIS) spectroscopy. The FTIR analysis indicated that Yb2O3 gate dielectrics post-annealing exhibited Yb-O bonding due to oxygen diffusion, as well as N-O bonding and NO3-bonding, demonstrating the formation of a nitrogen barrier at the interface to hinder oxygen diffusion. The optical band gap values of Yb2O3 gate dielectrics post-annealing ranged from 3.092 eV to 3.267 eV. Notably, the Yb2O3 gate dielectric annealed at 800 °C showed no breakdown within the 0–3 V range across all samples. The acquisition of a high k value of 19.40 and a low effective oxide charge (Qeff) of 5.32 x 1011 cm-2, along with the superior I-V characteristics, suggest that the Yb2O3 gate dielectric annealed at 800oC has the potential to be employed for next generation MOS applications.

Hetero dielectric based dual material gate AlGaN channel MISHEMT for enhanced electrical characteristics

Herein, we report an AlGaN channel metal insulator semiconductor high electron mobility transistor (MISHEMT) in dual material gate (DMG) architecture with two different dielectrics as gate insulator for enhancing the DC performance of the device. The use of a high-k dielectric material as gate insulator below gate metal 1 and a low-k dielectric below gate metal 2 results in significant threshold voltage variation along the channel. This contributes to improved average carrier velocity which in turn results in better current drive. The proposed device exhibits a peak current of 162 mA/mm at zero gate bias, whereas, the DMG and single material gate (SMG) AlGaN channel HEMTs offer currents of 137 mA/mm and 125 mA/mm respectively. The peak transconductances are about 24.66 mS/mm, 23.68 mS/mm and 22.71 mS/mm respectively for the proposed device, DMG and SMG HEMTs. The proposed device reduces the OFF current by an order of 106 compared to that of DMG HEMT.

Effect of oxygen plasma treatment on the properties of ALD hafnium oxide films

In this work, we studied the effect of processing hafnium oxide samples prepared by atomic layer deposition in a gas discharge plasma of a mixture of argon and oxygen in a ratio of 1:10. It has been shown that such treatment preserves the amorphous structure of the film and reduces the content of oxygen vacancies in the film. This is important for the use of the film in the gate dielectric of a transistor. Processing in plasma leads to a change in its properties, namely: an increase in density and refractive index, as well as a decrease in the intensity of emission bands that are associated with an oxygen vacancy. The plasma temperature and ion energy were determined from the argon emission spectra. The activation energy for the diffusion of oxygen ions in hafnium oxide films has been calculated to be 0.43 eV.

Electrically tunable graded photonic crystal lens based on graphene plasmons.

Controlling the nonlinear relationship between surface plasmon polariton (SPP) mode index and chemical potential of graphene can be used in the field of active transformation optics. Here, we propose an electrically tunable 2D Graded Photonic Crystal (GPC) lens based on graphene SPP platform. Our platform comprises a graphene monolayer integrated into a back-gated structure with nano-patterned gate insulators. When the chemical potential of the graphene surface is designed to operate in the nonlinear region, the designed GPC lens can be continuously transformed between a Maxwell's fish-eye lens and a Luneburg lens by tuning the gate voltage. The range of the lens background chemical potential for allowing this transformation is systematically studied. To compensate for the significant errors inherent in the conventional effective medium theory (EMT) during the homogenization of photonic crystals (PCs), we propose a generalized effective medium theory (GEMT). The validity and accuracy of this approach are verified through comparisons with true values (based on rigorous eigenvalue solutions) and EMT values. Due to its advantages of on-site controls and easy fabrication characteristics, the proposed graphene GPC provides a new way for practical on-chip light manipulation.

Impact of monolayer WS2 surface properties on the gate dielectrics formation by atomic layer deposition

Two-dimensional transition metal dichalcogenides (2D TMDs), such as MoS2 and WS2, have emerged as promising channel materials for future generation transistors. However, carbon-based surface contaminants pose a significant challenge in the formation of high-quality metal–oxide–semiconductor gate stacks for 2D TMDs. Carbon-based surface contaminants are known to be present even on directly grown 2D TMDs that have not been in contact with polymers. These organic contaminants affect precursor adsorption during atomic layer deposition (ALD) of gate dielectrics on 2D TMDs and as such the 2D-dielectric interface. This study examines the effectiveness of predeposition annealing in mitigating carbon-based contaminants while maintaining the integrity of a directly grown WS2 monolayer on a SiO2 substrate. We show that a WS2 monolayer on a SiO2/Si substrate remains stable during vacuum annealing at temperatures up to 400 °C. Water contact angle measurements and x-ray photoelectron spectroscopy confirm that the surface concentration of carbon starts to decrease at 150 °C. Thermal anneal improves the surface coverage of Al2O3 for both conventional chemisorption-based ALD and physisorbed-precursor-assisted ALD processes by facilitating more effective Al2O3 nucleation on the WS2 monolayer. The impact of predeposition anneal on the Al2O3 growth behavior in both processes can be explained by changes in surface contaminant levels. Our results underscore the importance of surface pretreatment in dielectric deposition on 2D TMDs and demonstrate that predeposition anneal is an effective method to enhance ALD-based dielectric deposition on directly grown 2D TMDs.

Analysis on density of states and ION/IOFF ratio of GaN/GaN-graphene nanoribbon tunnel FET for enhanced bio-sensing applications

Abstract This research introduces a new analytical model that studies the effect of ferro-dielectric on the operational performance of TFETs doped with halogens. The effect of source and drain depletions, voltage-drain & gate, thickness and capacitance of gate insulator are all investigated in this study. Accurate measurements of the surface potential are required to ascertain the transconductance, gate-to-drain capacitance, and lateral electric field of the device. Our model, which employs Ferroelectric Halo-Doped double gate (FHDD)-gated device designs, has been demonstrated to produce results that nearly match those produced from TCAD simulations. This was accomplished by doing a comparative analysis of the outcomes derived from both sets of simulations. Furthermore, the performance of the suggested structure of TFET, which integrates a dielectric of Fe and GaN heterostructure, surpasses that of other similar devices (fT) in terms of ON current, ON/OFF ratio, transconductance, and cut-off frequency. A ferroelectric dielectric was used to create a ferroelectric heterostructure. This study also centers on the creation and application of a graphene nanoribbon field effect transistor (GNR-TFET) to detect sugar molecules, specifically fructose, xylose, and glucose. The detecting signal is generated by utilizing the fluctuation in the electrical current of the GNR-TFET caused by the presence of individual sugar molecules. The GNR-TFET exhibits noticeable variations in the density of states, transmission spectrum, and current when exposed to individual sugar molecules. The sensor under investigation is being developed and examined using a combination of semi-empirical modeling and non-equilibrium Green's functional theory (SE + NEGF). According to the research, the modified GNR TFET has the ability to quickly and accurately detect individual sugar molecules in real-time.

Impact of bias stress and endurance switching on electrical characteristics of polycrystalline ZnO-TFTs with Al2O3 gate dielectric

Abstract This study experimentally investigates electrical characteristics and degradation phenomena in polycrystalline zinc oxide thin-film transistors (ZnO-TFTs). ZnO-TFTs with Al2O3 gate dielectric, Al-doped ZnO (AZO) source–drain contacts, and AZO gate electrode are fabricated using remote plasma-enhanced atomic layer deposition at a maximum process temperature of 190 °C. We employ positive bias stress (PBS), negative bias stress (NBS), and endurance cycling measurements to evaluate the ZnO-TFT performance and examine carrier dynamics at the channel-dielectric interface and at grain boundaries in the polycrystalline channel. DC transfer measurements yield a threshold voltage of −5.95 V, a field-effect mobility of 53.5 cm2/(V∙s), a subthreshold swing of 136 mV dec−1, and an on-/off-current ratio above 109. PBS and NBS measurements, analysed using stretched-exponential fitting, reveal the dynamics of carrier trapping and de-trapping between the channel layer and the gate insulator. Carrier de-trapping time is 88 s under NBS at −15 V, compared to 1856 s trapping time under PBS at +15 V. Endurance tests across 109 cycles assess switching characteristics and temporal changes in ZnO-TFTs, focusing on threshold voltage and field-effect mobility. The threshold voltage shift observed during endurance cycling is similar to that of NBS due to the contrast in carrier trapping/de-trapping time. A measured mobility hysteresis of 19% between the forward and reverse measurement directions suggests grain boundary effects mediated by the applied gate bias. These findings underscore the electrical resilience of polycrystalline ZnO-TFTs and the aptitude for 3D heterogeneous integration applications.

Investigation of the Electrical Characteristics of AlGaN/AlN/GaN Heterostructure MOS-HEMTs with TiO2 High-k Gate Insulator

This paper investigates the impact of TiO2 high-k gate insulator on the electrical characteristics of AlGaN/AlN/GaN MOS-HEMT transistors using MATLAB and Atlas-TCAD simulation software. The physical analytical model of the MOS-HEMTs is used for simulation from Al2O3, HfO2, and TiO2 as the gate dielectric materials, which provide higher performance and reliability of the MOS-HEMT devices. The device shows a good improvement in its result of the DC and AC characteristics with different permittivity of insulator materials. Thus, the DC and AC performance of GaN MOS-HEMTs is higher than with other insulators, such as Al2O3 and HfO2 by using TiO2 as the gate dielectric. Moreover, the simulation results proved that TiO2 is the better gate dielectric material to enhance the electrical reliability of the power switching devices for high-temperature applications such as electric automobiles.

Simulation study of a novel GaN on Si Quasi‐Vertical Reverse‐Conducting Insulated Gate Bipolar Transistor

Abstract In this paper, a novel GaN on Si quasi-vertical reverse conducting insulated gate bipolar transistor(RC-IGBT) with a new NPN structure is proposed and simulated by Silvaco TCAD. The distinctive feature of this structure lies in fabricating the original bottom P-Collector on the wafer surface. In comparison to conventional IGBT devices with PNPN structures, this NPN structure overcomes two major challenges: the difficulty in forming ohmic contacts due to the activation difficulty of the bottom P-GaN and the necessity of creating backside through-holes for electrode formation. Simultaneously, the N-GaN in the emitter and reverse-conducting regions can be selectively regrown through Metal-Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE), avoiding the etching effect of top-layer N-GaN on P-GaN during the fabrication of P-type electrodes. This approach demonstrates a high level of process feasibility. In this paper, Silvaco TCAD is used to simulate the static and dynamic characteristics of this novel quasi-vertical RC-IGBT device. The simulation results reveal that the device has a high saturation current(Ion,sat) density of 18224.67A/cm2 at Vge=14V,a threshold voltage (Vth) of 5V,a breakdown voltage of 828V,a latch-up voltage of 800V ,and a switching speed of nanoseconds. In addition, the selection of device parameters is studied in this paper.

Modeling and characterization of low frequency noise in self-aligned top-gate coplanar IGZO thin-film transistors

Abstract A modified low-frequency noise (LFN) model was proposed to accurately estimate the quality of the gate dielectric in self-aligned top-gate (SA TG) coplanar structure indium–gallium–zinc oxide (IGZO) thin-film transistors (TFTs). The proposed LFN model was derived by modifying the conventional carrier number with correlated mobility fluctuation model considering the peculiar characteristics of SA TG coplanar IGZO TFTs such as the channel length reduction due to the diffusion of hydrogen atoms or oxygen vacancies from the source/drain to the channel, as well as the relatively large source/drain parasitic resistance. The proposed model was validated by demonstrating that the measured LFN values were in good agreement with the predicted values from the proposed model for all SA TG coplanar IGZO TFTs with SiO2 gate dielectrics deposited under different plasma-enhanced chemical vapor deposition (PECVD) power densities. The near-interface gate dielectric trap densities extracted from each TFT using the proposed LFN model revealed a clear increase as the PECVD power increased, which is considered a major cause of poor positive-bias-temperature-stress stability of the SA TG coplanar IGZO TFT with SiO2 gate dielectric deposited under high PECVD power conditions.

Comparing post-deposition and post-metallization annealing treatments on Al2O3/GaN capacitors for different metal gates

Vertical Metal–Insulator–Semiconductor (MIS) capacitors with an Al2O3 thin film as a gate insulator have been fabricated on homoepitaxial GaN-on-GaN samples. The effect of the annealing treatments on the MIS characteristics has been investigated exploring two different approaches: Post-insulator-Deposition-Annealing (PDA) and Post-gate-Metallization-Annealing (PMA), i.e., annealing on the bare Al2O3 layer and annealing after the gate metallization deposition on Al2O3. The direct comparison between PDA and PMA is crucial to understand the impact of the metal/dielectric interface quality on the behavior of the Al2O3/GaN MIS capacitors. The efficacy of annealing has been monitored as a function of metal gates having different work functions: nickel (Ni), molybdenum (Mo), and tantalum (Ta). It has been found that both PDA and PMA approaches are equally able to improve the Al2O3/GaN interface electrical quality. However, the PMA demonstrates an additional beneficial effect on the metal/Al2O3 interface. In particular, the possible chemical reactions activated by the annealing process at the metal/dielectric interface can perturb the known metal/dielectric dipole responsible for Fermi-level pinning phenomena, causing a positive shift of the flat voltage (VFB), which depends on the metal, and approaching the theoretical value in the case of Mo and Ta.

Synergistic Effects of Deposition Temperatures for Active and Gate Insulator of Top-Gate Thin-Film Transistors Using InGaZnO Channels Prepared by Thermal Atomic-Layer Deposition

Synergistic Effects of Deposition Temperatures for Active and Gate Insulator of Top-Gate Thin-Film Transistors Using InGaZnO Channels Prepared by Thermal Atomic-Layer Deposition

Fabrication of Electrospun Porous TiO2 Dielectric Film in a Ti–TiO2–Si Heterostructure for Metal–Insulator–Semiconductor Capacitors

The development of metal–insulator–semiconductor (MIS) capacitors requires device miniaturization and excellent electrical properties. Traditional SiO2 gate dielectrics have reached their physical limits. In this context, high-k materials such as TiO2 are emerging as promising alternatives to SiO2. However, the deposition of dielectric layers in MIS capacitors typically requires high-vacuum equipment and challenging processing conditions. Therefore, in this study, we present a new method to effectively fabricate a poly(vinylidene fluoride) (PVDF)-based TiO2 dielectric layer via electrospinning. Nano-microscale layers were formed via electrospinning by applying a high voltage to a polymer solution, and electrical properties were analyzed as a function of the TiO2 crystalline phase and residual amount of PVDF at different annealing temperatures. Improved electrical properties were observed with increasing TiO2 anatase content, and the residual amount of PVDF decreased with increasing annealing temperature. The sample annealed at 600 °C showed a lower leakage current than those annealed at 300 and 450 °C, with a leakage current density of 7.5 × 10−13 A/cm2 when Vg = 0 V. Thus, electrospinning-based coating is a cost-effective method to fabricate dielectric thin films. Further studies will show that it is flexible and dielectric tunable, thus contributing to improve the performance of next-generation electronic devices.

Functional Zwitterionic Polyurethanes as Gate Dielectrics for Organic Field‐Effect Transistors

AbstractThe development of polymeric dielectrics with a high dielectric constant is of great significance for flexible low‐voltage organic field‐effect transistors (OFETs). Herein, functional polyurethanes (PUs) with nitro and sulfobetaine zwitterionic groups are synthesized, and their electrical properties, mechanical properties, and the performances of OFET devices using these zwitterionic PUs as gate dielectrics are studied. Compared with sulfobetaine zwitterion‐containing PUs, nitro‐containing PUs (NO2‐PUs) show higher dielectric constant up to 6.5. Both zwitterionic PUs enhance the OFET performances, while the effect of NO2‐PU is more significant. Devices using NO2‐PU‐15 that contains 15 moL% nitro groups as the dielectric layer show the best performance and a threshold voltage (Vth) of as low as −0.02 V together with two orders’ increase of the mobility is observed, compared with the devices using PU without nitro groups. This study provides a new method to improve the dielectric constant of polymeric dielectrics, which is valuable for flexible/stretchable and wearable electronic devices.

An IGBT coupling structure with a smart service life reliability predictor using active learning

Abstract An effective approach is proposed to evaluate the service life reliability of a multi-physics coupling structure of an insulated gate bipolar transistor (IGBT) module. The node-based smoothed finite element method with stabilization terms is firstly employed to construct an electrical-thermal-mechanical (ETM) coupling structure of the IGBT module, based on which the multi-physics responses can be accurately calculated to predict the service life of the IGBT module. By using the high-quality sample data obtained through the ETM coupling model, a Monte Carlo based active learning Kriging metamodel (AK-MCS) is developed to assess the service life reliability of the IGBT module, which can greatly reduce the computational cost needed by the surrogate model construction and reliability analysis. Numerical results show that the proposed ETM coupling structure can produce high-quality sample data of the IGBT dynamics and the AK-MCS machine learning technique can accurately estimate the service life reliability of the IGBT module.