Customer need for faster electronic products, with enhanced functionalities and smaller form factor is driving the growth of the microelectronic industry. As the traditional more Moore approach is slowing down due to the exponential cost of silicon scaling and the lowers yields [1], a chiplet-based future is being adopted [2, 3]. Chiplets enable modular products by combining chips from various technologies and technology nodes, allowing designs out of reach of the monolithic approach [4, 5]. To tackle the inherent interconnect latency observed in the 2.5D-System-on-Chip (SoC) approach, 3D interconnects technologies are a must.Nevertheless, to enable advanced 3D-SoC circuits, the 3D interconnect pitch needs to be scaled further. This can be achieved using Through Silicon Vias (TSV) [6-8] and wafer-to-wafer (W2W) hybrid bonding [9, 10], in combination with nano-TSVs connecting back-side buried power rails [11]. While TSVs are used to electrically connect the front side to the back side of a silicon wafer, and thus to enable die stacking, W2W hybrid bonding connects directly two wafers through copper pads embedded in a dielectric material which is generally SiO2 [12, 13] or SiCN [14].Unfortunately, these novel technologies come along with key reliability issues. TSV’s aggressive aspect ratios (up to 20:1 [15]) put stringent requirements on the etch and liner deposition process to guarantee the electrical isolation and avoid copper diffusion in the silicon substrate [16]. Additionally, their sole presence has been shown to influence the reliability of the above BEOL layers [17, 18] and near-by transistors [6]. In the hybrid-bonding technologies, the constant pitch down-scaling results in an increased leakage current along the bonding interface [19] which can be further enhanced by pad-to-pad misalignment [20]. While this misalignment can be mitigated with unequal pad schemes [21], the resulting copper-dielectric interface could lead to metal ion drift at elevated temperature and electric fields [19].In this presentation, the reliability issues and failure mechanisms linked to 3D technologies will be discussed and a particular focus will be given on topics which are currently of interest at imec. The controlled-IV methodology, used to assess dielectric material reliability will be reintroduced. Data obtained on 1 x 5 µm TSVs will demonstrate the advantage of imec embedded barrier to mitigate reliability issues arising from copper resputtering during the etch process while the importance of an optimized etch recipe will be shown. Reliability characterizations of SiCN-based hybrid bonded structures, down to a pitch of 700 nm will be presented along with a discussion on the influence of the CMP process on the leakage current and resulting lifetime. The potential influence of copper ion diffusion along the bonding interface will be analyzed. Finally, the impact of electromigration on the copper pads will be presented.[1] Samavedam, S. B. et al., IEDM, 2020.[2] Cao, L., IEDM, 2022.[3] Beyne, E. et al., IEDM, 2021.[4] Su, L. et al., IEDM, 2017[5] Naffziger, S.et al., IEEE ISSCC, 2020.[6] Croes, K., et al., IEEE Design & Test , 2016, Vol. 33, No. 3.[7] Burkett, S. et al., Journal of Vacuum Science & Technology A, 2020, Vol. 38, No. 3.[8] Van Huylenbroeck, S. et al., ECTC, 2019.[9] Jouve, A. et al., SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2017.[10] Kim, S-W. et al., ECTC, 2020.[11] Jourdain, A. et al., ECTC, 2022.[12] Utsumi, J., et al., Micro and Nano Engineering, 2019, Vol. 2[13] Ayoub, B et al., EPTC, 2020.[14] Iacovo, S. et al., ECTC, 2022.[15] Van Huylenbroeck, S et al., IEEE 3DIC, 2016[16] Li, Y. et al., Microelectronics Reliability, 2013, Vol. 54, No. 9-10[17] Frank, T. et al., Microelectronics Reliability, 2013, Vol. 53, No. 1[18] Li, Y. et al., IRPS, 2014.[19] Hou, Lin et al., IRPS, 2022.[20] Ayoub, B. et al., IRPS, 2022.[21] Kim, S-W., et al., ECTC, 2020.
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Nov 1, 2024
Zhourui Zhang + 10
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