Instruction Set Research Articles

Multiple-Baseline Design Study of Deliberate Practice for Learning Psychotherapeutic Techniques

ABSTRACT Deliberate practice is a framework for expertise development that has been applied in many fields but rarely to studies of psychotherapy skill development. The current multiple-baseline study sought to examine the effects of deliberate practice on initial psychotherapy skill acquisition in three completely novice students. In addition to quantitative measures of performance, qualitative feedback concerning their methods of orienting to tasks was also collected regularly. Participants were given a minimal set of instructions to conduct and record psychotherapy role-play exercises, two of whom were provided with opportunities for focal deliberate practice beginning after their 3rd or 5th sessions. Results indicated that deliberate practice was associated with rapid, precipitous increases in reliably coded, structured evaluation of skill, which in many cases approached the cutoff for competent professional CBT practice. The potential of these methods to enhance learning and establish lifelong methods of skill improvement at all performance levels is discussed.

Design a 5-stage pipeline RISC-V CPU and optimise its ALU

The RISC-V instruction set has advanced and expanded significantly in recent years. It is an open instruction set architecture (ISA) based on the concept of Reduced Instruction Set Computing (RISC). This article uses Verilog to design a 5-stage pipeline CPU based on RISC-V architecture in Vivado 2022.2. The CPU can execute 38 instructions and optimises its arithmetic logic unit (ALU) by optimising adders, shifters, and multipliers. Next, write a testbench in the simulation software to verify the functionality of the CPU. RTL diagrams and reports are then generated to verify the design structure and evaluate resource allocation. Finally, the CPU successfully executes the instruction and obtains the correct operation result, and the occupation of LUT resources in the shifter part is reduced. This work serves as an important reference for system-on-chip (SoC) and computer design in general. It not only highlights the potential of the RISC-V architecture but also demonstrates the success of optimisation efforts. This paves the way for more powerful and efficient computing systems.

The Consciousness of Acting: The Effect of Divided and Unified Consciousness on Acting Performance

The art of acting, drama, or theatre has been largely excluded from the debate on the nature of consciousness in the scientific community. The purpose of this study was to investigate whether acting performance benefits from a divided or unified state of consciousness. Twenty-four acting students and professionals performed a monologue three times, twice with an interference task. Two different sets of instructions were provided for this task: one that asked participants to incorporate the interference into the world of their monologue (unified consciousness), and another that asked them to dissociate it from their theatrical performance (divided consciousness). The variables studied included an evaluation of performance on primary and secondary tasks, as well as responses on a creativity and dissociative experiences questionnaire and to open-ended questions. Two acting professors provided monologue ratings. There was a significant difference in interference task performance scores for the divided and unified conscious conditions, as well as for the primary rater's monologue scores. Participants performed better on both tasks when they were asked to incorporate the interference into the imagined world of their monologue. These results show that a unified conscious approach results in better performance on certain tasks, implying that unified consciousness may be more adaptive for certain daily functions such as multitasking.

A Conv‐GEMM reconfigurable accelerator with WS‐RS dataflow for high throughput processing

AbstractConvolution and matrix operations are both important computations in Deep Neural Networks (DNNs). However, the significant differences between convolution and matrix computation patterns have posed a challenge in efficiently supporting both convolution (Conv) and general matrix multiplication (GEMM) on hardware design. This paper proposes a Conv‐GEMM reconfigurable accelerator architecture for high throughput edge processing. A weight stationary‐row streaming (WS‐RS) dataflow scheme is proposed, which maximizes data reuse through hierarchical memory structures and flexible PE connections, and supports high throughput edge‐based deep learning algorithms. Based on the proposed dataflow, multi‐scale memory access network (MMAN), reconfigurable accumulator array (RAA), and configurable instruction set architecture (ISA) are designed to optimize computation throughput and energy efficiency. The accelerator is designed under 65 nm technology, achieves peak performance of 1.15 TOPS at 250 MHz, with an energy efficiency of 1.14 TOPS/W. The GEMM computation achieves 85.7% latency improvement and the Mobilenet‐V1 processing achieves a throughput of 529 fps under a 256 × 224 image size and an 87.15% (top‐5) accuracy on the ImageNet dataset.

Fault tolerance evaluation study of a RISC-V microprocessor for HEP applications

The utilization of a radiation-hard microprocessor or a System-on-Chip (SoC) design methodology significantly benefits the future design of ASICs for HEP experiments. To evaluate the fault tolerance of a radiation-hard design, it is important to obtain detailed information on the soft error rate and contributing factors. This article presents a simulation-based approach to investigate the effects of faults induced by single event transients in a microprocessor based on the open RISC-V instruction set architecture.

Engaging Turkish Learners in Digital Participatory Culture Through Social Media?Enhanced Language Instruction

Research has shown that social media can provide valuable tools for L2 teaching and learning, particularly for developing learners’ informal learning of non-academic interactional registers, socio-pragmatics, culture, and multiliteracies. However, the fact that their benefits are more pronounced in informal contexts due to their quotidian nature poses a challenge for incorporating them into formal language instruction settings. In response, we designed social media-enhanced instruction for 12 intermediate-level learners of Turkish as a foreign language at a large public American university. Learners were required to post tweets in Turkish and engage with both their colleagues and native speakers of Turkish on Twitter each week, writing biweekly journal entries about their experiences. A mixture of quantitative and qualitative data, consisting of learners’ journal entries, tweets, and the projects they developed as part of the instruction, were collected before, during, and after instruction and then analyzed using grounded qualitative techniques. The findings provide insight into how Turkish learners can engage in various social media literacy practices, developing awareness of everyday Turkish cultural discourses and language uses. The findings highlight the potential of social media-enhanced language learning as a means to engage in digital participatory culture.

A Survey on IEEE 1588 Implementation for RISC-V Low-Power Embedded Devices

IEEE 1588, also known as the Precision Time Protocol (PTP), is a standard protocol for clock synchronization in distributed systems. While it is not architecture-specific, implementing IEEE 1588 on Reduced Instruction Set Computer-V (RISC-V) low-power embedded devices demands considering the system requirements and available resources. This paper explores various approaches and techniques to achieve accurate time synchronization in such instruments. The analysis covers software and hardware implementations, discussing each method’s challenges, benefits, and trade-offs. By examining the state-of-the-art in this field, this paper provides valuable insights and guidance for researchers and engineers working on time-critical applications in RISC-V-based embedded systems, aiding in selecting the most-suitable stack for their designs.

Understanding performance responses: Instructional transitions in musical masterclasses

This paper extends analysis of the ‘assessment receipt’ to include talk and embodied interaction during ‘performance responses’ in music masterclass interactions. By grounding the analysis in questions of performance completion and audience applause onset, it details the utility of variously position assessment tokens, during performance, before applause, during applause and after applause. These different verbal assessment positions afford, in different ways, instructional interaction by situating the instructor as next relevant speaker. They also help coordinate performance completions and audience applause onset. The paper also identifies the ‘receipt assessment’, which reverses the component ordering of the earlier phenomenon. The paper is relevant to those studying performance as interaction and extends and deepens the growing insights into musical instructional settings.

A Novel Multidimensional Tensile, Shear, and Buckling Sensor for the Measurement of Flexible Fibrous Materials.

To meet the complex and diverse demands for low-stress mechanical measurements of fabrics and other flexible materials, two integrated multidimensional force sensors with the same structure but different ranges were explored. They can support both rapid and precise low-noise, high-precision, low-cost, easy-to-use, reliable, and intelligent solutions for the complex measurement of fabric mechanics. Having analysed the mechanical relationship of the parallel beam theory, and considering the specific requirements of fabric measurement, a novel multi-dimensional force sensor is designed, capable of measuring tensile, shear, and buckling properties. Finite element analysis is used to simulate the mechanical performance of this sensor for fabric-loading/unloading measurement, and the sensitivity of the mechanical quantity transfer, the amount of sensor deformation, the stress distribution, and the degree of inter-dimensional coupling have been investigated and verified. The basis for subsequent digital processing is achieved by a low-offset, low-temperature-drift, low-power-consumption analogue front end, 24-bit ADC circuit, and signal conditioning electronics, suitable for the measurement of fabric mechanics under low stress, which is like the end-user requirements. The sensor information channel is supported by a host microcontroller with a DSP and a floating-point processing instruction set. Information processing is performed in time-sharing with the support of a multitasking real-time operating system. The purpose of designing this sensor is to facilitate the development of a new testing instrument, which will adopt the advances of current instruments whilst eliminating their shortcomings.

Model-based, fully simulated, system-level power consumption estimation of IoT devices

Internet of things (IoT) gaining more importance due to its crucial role in pervasive computing and also Industry 4.0. Since the number of IoT devices is scaling up to multiple dozens of billions, the importance of energy efficiency is significantly increased. With the consideration of huge variety of IoT device hardware and software, a comprehensive model and estimation methodology on energy consumption is necessary as an enabler. IoT devices are also frequently updated, upgraded and maintained because of the evolving nature of the requirements and market demands. Each and every such operation has an effect on the power consumption and arose the necessity for a new energy consumption modeling and estimation. This process is applicable for development of IoT devices, as well as the maintenance phase. Since the variety of designs is unlimited, and battery capacity is usually fixed, or a cost factor, a generic, fully simulated, model-based energy consumption estimation of IoT devices is crucial. In this study, we aim to address this problem via proposing fully simulated, model-based, system-level power estimation approaches, as well as their success rate in typical real-life scenarios. It can be seen that the proposed methodology has high accuracy over %97. For the realization of the best-proposed approach, we used Open Virtual Platform (OVP) as an instruction set accurate simulator.

SimuQ: A Framework for Programming Quantum Hamiltonian Simulation with Analog Compilation

Quantum Hamiltonian simulation, which simulates the evolution of quantum systems and probes quantum phenomena, is one of the most promising applications of quantum computing. Recent experimental results suggest that Hamiltonian-oriented analog quantum simulation would be advantageous over circuit-oriented digital quantum simulation in the Noisy Intermediate-Scale Quantum (NISQ) machine era. However, programming analog quantum simulators is much more challenging due to the lack of a unified interface between hardware and software. In this paper, we design and implement SimuQ, the first framework for quantum Hamiltonian simulation that supports Hamiltonian programming and pulse-level compilation to heterogeneous analog quantum simulators. Specifically, in SimuQ, front-end users specify the target quantum system with Hamiltonian Modeling Language, and the Hamiltonian-level programmability of analog quantum simulators is specified through a new abstraction called the abstract analog instruction set (AAIS) and programmed in AAIS Specification Language by hardware providers. Through a solver-based compilation, SimuQ generates executable pulse schedules for real devices to simulate the evolution of desired quantum systems, which is demonstrated on superconducting (IBM), neutral-atom (QuEra), and trapped-ion (IonQ) quantum devices. Moreover, we demonstrate the advantages of exposing the Hamiltonian-level programmability of devices with native operations or interaction-based gates and establish a small benchmark of quantum simulation to evaluate SimuQ's compiler with the above analog quantum simulators.

Design of RISCV processor using verilog

The main goal of this paper is to develop a 32-bit pipelined processor with several clock domains based on the RISCV (open source RV32I Version 2.0) ISA. To minimize the complexity of the instruction set and speed up the execution time per instruction, a RISC (Reduced Instruction Set Computer) processor that uses less hardware than a CISC (Complex Instruction Set Computer) is used. Furthermore, this paper constructed this processor with five levels of pipelining with the aid of necessary block diagrams, and all of the processes are well described. In this paper, a RISCV processor is designed and simulated using Verilog. The design of the RISCV processor provides an alternative for software and hardware design to the computer designers as it provides free and open instruction set architecture (ISA). Besides, the designed RISCV processor will be using 5-stage pipeline techniques to improve the overall performance of the processor. This system is started by implementing several main modules, such as alu, aludec, maindec, imem, dmem, regfile, pc_mux, result_mux, pipeline register (IF/ID, ID/IEx, IEx/IMem, and IMem/IW), forwardMuxA, and forwardMuxB. Besides, a hazard unit is implemented into the design to mitigate hazard conditions. The functionality of these modules was simulated and verified by using Xilinx Vivado software.

Overcoming linguistic barriers in code assistants: creating a Qlora adapter to improve support for russian-language code writing instructions

This article describes an approach to learning and evaluating an adapter model for the popular zephyr-7b-beta language model. The adapter was designed to improve the performance of the basic model in tasks related to programming and understanding the Russian language. Taking into account the high quality of the original model's work in problems in English, the purpose of the study was to expand its linguistic and technical spectrum. The proposed adapter was trained using a large and diverse dataset, including question-answer pairs related to programming, as well as a text with a discussion of the code in Russian. The applied training methodology ensures an improvement in the quality of the model's responses in understanding and generating Python code based on Russian-language instructions. The authors evaluated the performance of the basic model with the adapter installed using various metrics, comparing it with the basic model, as well as with other advanced models in this area. The results obtained by the authors showed significant improvement both in tasks related to writing Python code and in processing the Russian language, confirming the effectiveness of the proposed adapter. The analysis of the experiment results showed that the adapter not only adds new functionality to the model but also significantly changes the priority of the model's output in favor of the instructions that were included during the retraining stage. To eliminate the fact of changing the model's output priority mentioned above, the following methods are proposed: 1) Using a different format for writing the query (prompt) when formatting the dataset for training the model, different from the original format in Zephyr. 2) Including instructions from the first stage of fine-tuning (retraining) in the instruction set. 3) Creating a "mixture of experts" from several different models, where each model will specialize in the most accurate solution to one or several tasks from the overall range of solvable tasks. The methods of retraining the model without losing the original characteristics are promising directions for future research in the field of resource-efficient modification of large language models. In the conducted experiment, a large language model "HuggingFaceH4/zephyr-7b-beta" was successfully fine-tuned (using the QLoRA adapter creation method) to improve its capabilities in writing Python code based on Russian instructions and providing explanations in Russian. The testing results showed that when the created adapter is installed, the model's text generation priority shifts towards generating code with explanations. Synthetic tests also demonstrated significant improvements in the model's ability to solve programming and mathematical problems. Therefore, it is advisable to consider the possibility of changing adapters depending on the type of task being solved. Changing the adapter installed on the model (loaded into memory) does not take a significant amount of time, which allows for the creation of a set of adapters tailored to specific tasks and their interchange based on the type of tasks being solved. Changing adapters instead of models eliminates the need to load multiple full versions of the model into the memory of the computational accelerator, which, depending on the implementation method, either significantly reduces the use of memory or the model loading time. Thus, the use of adapters speeds up training and optimizes the utilization of computational resources during model operation. This presented research contributes to the current efforts in the field of machine learning and natural language processing towards creating more versatile AI models. The observed potential of adapter models in improving the quality of responses in specific domains without the need for extensive retraining helps meet the growing demand for models for multilingual natural language processing and code generation. In the conducted experiment, an assessment was made of the possibility of retraining a model that had already been trained on a set of instructions. The methods of additional training of a language model with new instructions without losing the ability to perform original instructions are not well-studied, which is why a decision was made to test the feasibility and effectiveness of such retraining. Based on the description of the LoRA method, this approach is possible because during such training, the original weights of the model remain unchanged and are only supplemented with new coefficients from the adapter model (the total number of weights equals that of the base model), which was trained on new instructions. The experiment determined that multilingual adaptation of language models is viable, and that it also could be implemented using parametrically efficient methods on comparatively low-end hardware.

A Structured Approach to Mentoring Tertiary Level Entrepreneurship Students: A Literature Review

The form, structure, and manner of mentorship engagement in industry and colleges have been presented in some literature as discreet, disparate, and sometimes ad hoc events. This paper sought to establish the dominant form, structure, and coherent approach to mentorship that would form the basis for adoption, with appropriate adaptation, for entrepreneurship training in tertiary colleges in Kenya. Specifically, this study sought to delineate specific functions of mentorship in the instruction of entrepreneurship students; examine the nature of engagement of mentor and mentee in the mentoring relationship within an instructional setting; and explore the relationship between mentorship and graduate entrepreneurship student business outcomes. The study was based on a desk review of literature covering key publications on mentoring and articles published in the last 40 years and available at libraries, the internet, and databases. The review has identified functions, forms and models, settings, resources, accountability structures, and outcomes that would persuade colleges in Kenya to adopt and modify to suit their specific situations to achieve effective mentorship results.

On Modeling and Detecting Trojans in Instruction Sets

On Modeling and Detecting Trojans in Instruction Sets

Effect of coaching the sit-to-stand motion and attentional focus.

[Purpose] The present study investigated whether (1) "standing up while bowing" is effective for promoting the sit-to-stand (STS) motion and (2) whether this coaching promotes internal focus. [Participants and Methods] The participants included 17 healthy adults who performed the 30-s chair stand test with two sets of verbal instructions. The verbal instructions were as follows: "Please stand up as many times as possible for 30 s" (control condition) and "Please stand up while bowing as many times as possible for 30 s" (bowing condition). The participants performed the tests successively under the two conditions. In the 30-s chair stand test, a three-axis accelerometer was attached to the participants and the sagittal STS motion was filmed using a video camera. After the 30-s chair stand test, we used the modified Movement-Specific Reinvestment Scale (MSRS) to evaluate attentional focus. Differences in the measurements were analyzed using the Wilcoxon signed-rank test or paired t-test for each condition. [Results] Statistical analysis revealed significant differences in the CS-30 count, time from sitting to standing, time from sitting to lift-off, time from lift-off to standing, and the trunk tilt angle on lift-off. Regarding the questionnaire, Statistical analysis revealed significant differences in the MSRS and "conscious motor processing". [Conclusion] These results suggest that "standing up while bowing" has limited effectiveness in promoting the STS motion because the coaching promotes internal focus.

Acoustic metasurfaces with Frieze symmetriesa).

Frieze patterns follow a set of tiling instructions including reflection, rotation, and translation, and tile the infinite strip. Many metamaterials function due to the underlying symmetry, and its strategic breaking, of their constituent sub-structures that allow tailoring of the dispersion of modes supported by the structure. We design, simulate, and experimentally characterize seven one-dimensional acoustic metasurfaces whose unit cells each belong to one of the distinct Frieze groups.

SPC5: An efficient SpMV framework vectorized using ARM SVE and x86 AVX-512

The sparse matrix/vector product (SpMV) is a fundamental operation in scientific computing. Having access to an efficient SpMV implementation is therefore critical, if not mandatory, to solve challenging numerical problems. The ARMbased AFX64 CPU is a modern hardware component that equips one of the fastest supercomputers in the world. This CPU supports the Scalable Vector Extension (SVE) vectorization technology, which has been less investigated than the classic x86 instruction set architectures. In this paper, we describe how we ported the SPC5 SpMV framework on AFX64 by converting AVX512 kernels to SVE. In addition, we present performance results by comparing our kernels against a standard CSR kernel for both Intel-AVX512 and Fujitsu-ARM-SVE architectures.

Using the Saga design pattern for transaction management in a microservice architecture

The use of microservice architecture in software development, in which each service is a self-sufficient participant with its own area of responsibility, its own data store, set of technologies, and work environment, is challenging in the context of transactions in a distributed service mode. After all, from the point of view of reliability and integrity of the system, it is extremely important to ensure data consistency, which implies compliance with defined restrictions and rules, absence of contradictions and consistency of data between system components. The architecture built on microservice interaction provides capabilities for decomposition of complex tasks, operational implementation of new functionality, isolation of critical components and scaling of individual software components. As a rule, the microservice architecture implements the principle «Database per service» — an approach according to which each microservice uses its own database, instead of a single shared database, as is usually implemented in a monolithic architecture. To ensure data consistency, the SAGA design pattern can be used, which provides a set of instructions for the correct management of transactions in a distributed architecture. To avoid the use of distributed transactions, it is recommended to use the SAGA design pattern, which allows for global data consistency through sets of local and compensating transactions. The template is fault-tolerant and ensures system reliability and integrity.

Evaluation of COVID-19 Vaccination Websites Using the DISCERN Tool and QUality Evaluation Scoring Tool

Abstract Background: This article aimed to evaluate the COVID-19 vaccine registration website across UN-recognized member states for their portal quality, reliability, ease of use, and help to the general population in informed decision-making. Methods: Twelve UN member states (countries) were selected based on the inclusion and exclusion criteria mentioned in the Methodology section of this article. The PPS technique was used for the sampling and selection of 12 countries from 193 UN member states. Post selection of UN member states, the study used two-step evaluation techniques, Step 1 – the DISCERN checklist consists of 16 questions in three sections and is aimed to assess the reliability of information and quality of information; Step 2 – The QUality Evaluation Scoring Tool (QUEST) consists of 6 items with a subitem, authorship, attribution, conflict of interest, complementarity, currency, and tone. The authors developed a standard set of instructions for evaluating vaccination portals to bring uniformity in understanding and context setting. Results: The DISCERN tool’s overall reliability score on the Likert scale of 0–5 was 4 (standard deviation [SD] ±1.28). On the quality of information regarding treatment choices, the average score was 3.4 (SD ± 1.67). The QUEST on ease of use, concision, and comprehensiveness demonstrated an average score of 18.1 (SD ± 8.3) out of 28. The vaccine registration portal of the Czech Republic was found to be the most informative and was able to provide scientifically valid information on safety, efficacy, long-term and short-term effects, and choice of vaccine with attributable authors’ details. India, Bangladesh, Nigeria, and South Africa scored relatively low for missing critical information on the website. The United Arab Emirates, the Republic of South Korea, Indonesia, Australia, and Argentina had minor elements missing. Conclusions: COVID-19 vaccination portals vary in the quality of information, and many were found unable to provide critical information for decision-making on getting vaccinated.