Instruction Memory Research Articles

A New Compiler for Space-Time Scheduling of ILP Processors

the exploitation of potential performance of superscalar processors has shown that processor is fed with sufficient instruction bandwidth. The fetcher and the Instruction Stream Buffer (ISB) are the key elements to achieve this target. Beyond the basic blocks, the instruction stream is not supported by current ISBs. The split line instruction problem depreciates this situation for x86 processors. With the implementation of Line Weighted Branch Target Buffer (LWBTB), the advance branch information and reassembling of cache lines can be predicted by the ISB. The code generation for parallel register share architecture involves some issues that are not present in sequential code compilation and is inherently complex. To resolve such issues, a consistency contract between the code and the machine can be defined and a compiler is required to preserve the contract during the transformation of code. We want to achieve high level parallelism at faster clock speed it require distribution of processor resource and avoiding primitive that require single cycle global communication. Distribution of its resources, including instruction stream, register files, memory port and ALUs, over a pipelined two dimensional mesh interconnect are done by raw microprocessor (4). In this paper, we propose a compiler RPCC for general purpose sequential programs on the raw machine.

Partitioning and Allocation of Scratch-Pad Memory for Energy Minimization of Priority-Based Preemptive Multi-Task Systems

Energy minimization has become one of the primary goals in the embedded real-time domains. Consequently, scratch-pad memory has been employed as partial or entire replacement for cache memory due to its better energy efficiency. However, most previous approaches were not applicable to a preemptive multi-task environment. We propose three methods of partitioning and allocation of scratch-pad memory for fixed-priority-based preemptive multi-task systems. The three methods, i.e., spatial, temporal, and hybrid methods, achieve energy reduction in the instruction memory subsystems. With the spatial method, each task occupies its exclusive space in scratch-pad memory. With the temporal method, the running task uses entire scratch-pad space. The content of scratch-pad memory is swapped out as a task executes or gets preempted. The hybrid method is based on the spatial one but a higher priority task can temporarily use the space of lower priority task. The amount of space is prioritized for higher priority tasks. We formulate each method as an integer programming problem that simultaneously determines (1) partitioning of scratch-pad memory space for the tasks, and (2) allocation of program code to scratch-pad memory space for each task. Our methods not only support the real-time task scheduling but also consider aggressively the periods and priorities of tasks for the energy minimization. Additionally, we implement an RTOS-hardware cooperative support mechanism for runtime code allocation to the scratch-pad memory space. We have made the experiments with the fully functional real-time operating system. The experimental results have demonstrated the effectiveness of our techniques. Up to 73% energy reduction compared to a conventional method was achieved.

The effects of spatial representation on memory for verbal navigation instructions

Three experiments investigated effects of mental spatial representation on memory for verbal navigation instructions. The navigation instructions referred to a grid of stacked matrices displayed on a computer screen or on paper, with or without depth cues, and presented as two-dimensional diagrams or a three-dimensional physical model. Experimental instructions either did or did not promote a three-dimensional mental representation of the space. Subjects heard navigation instructions, immediately repeated them, and then followed them manually on the grid. In all display and experimental instruction conditions, memory for the navigation instructions was reduced when the task required mentally representing a three-dimensional space, with movements across multiple matrices, as compared with a two-dimensional space, with movements within a single matrix, even though the words in the navigation instructions were identical in all cases. The findings demonstrate that the mental representation of the space influences immediate verbatim memory for navigation instructions.

Directed forgetting shares mechanisms with attentional withdrawal but not with stop-signal inhibition

To explore the mechanisms underlying the ability to intentionally forget, the present study combined an item-method directed forgetting paradigm with tasks that measure stop-signal inhibition (Experiments 1 and 2) and inhibition of return (IOR; Experiment 2). Following each study-phase instruction to remember (R) or forget (F), a target was presented centrally (Experiment 1) or to the left or right in the visual periphery (Experiment 2); the target required a speeded response that was sometimes countermanded by a central stop signal. Although stop-signal reaction times were unaffected by the preceding memory instruction (or relationship with word-target location), F instructions improved stopping and delayed responses. Replicating previous findings in the literature, significant IOR was observed following F instructions but not following R instructions (Experiment 2). These findings suggest that intentional forgetting is an active cognitive process that more likely engages attentional mechanisms related to orienting than those related to stop-signal inhibition.

Keeping an eye on the truth: Pupil size, recognition memory and malingering

Background: Estimates of the incidence of malingering in patient populations vary from 1 to 12%, rising to ∼25% in patients seeking financial compensation. Malingering is particularly difficult to detect when patients feign poor performance on neuropsychological tests (see Hutchinson, 2001). One strategy to detect malingering has been to identify psychophysiological markers associated with deception. Tardif, Barry, Fox and Johnstone (2000) used electroencephalogram (EEG) recording to measure event related potentials (ERPs) during a standard recognition memory test. Previous research has documented an ERP “old/new effect” – late positive parietal ERPs are larger when participants view old, learned words compared to new words during recognition. Tardif et al. reasoned that if this effect is not under conscious control, then it should be equally detectable in people feigning amnesia as in participants performing to their best ability. As predicted, they found no difference in the magnitude and topography of the old/new ERP effect between participants who were asked to feign amnesia whilst performing the test and those asked to perform to their best ability. Whilst this approach shows some promise, EEG is comparatively time consuming and expensive. Previous research has shown that during recognition memory tests, participants' pupils dilate more when they view old items compared to new items (Otero, Weeks, and Hutton, 2006; Vo et al., 2008). This pupil “old/new effect” may present a simpler means by which to establish whether participants are feigning amnesia. Method: We used video-based oculography to compare changes in pupil size during a recognition memory test when participants were given standard recognition memory instructions, instructions to feign amnesia and instructions to report all items as new. Due to constant fluctuation in pupil size over time, and variation between individuals, a pupil dilation ratio (PDR) was calculated that represented the maximum pupil size during the trial as a proportion of the maximum during baseline. Results: Participants' pupils dilated more to old items compared to new items under all three instruction conditions (F(1.25) = 47.02, MSE < 0.001, p < .001, ηp2 = .65). There were no significant differences between baseline pupil size (F(1.63,40.76) = 1.90, p = .17, ns). Conclusions: The finding that under standard recognition memory instructions, participants' relative increase in pupil size is greater when they view old items compared to new items replicates previous research documenting the pupil old/new effect. That the effect persists, even when participants give erroneous responses during recognition, suggests that the “pupil old/new effect” is not under conscious control and may therefore have potential use in clinical settings as a simple means with which to detect whether patients are feigning amnesia.

Novel lineup methods for improving the performance of older eyewitnesses

AbstractPrevious research shows that older witnesses demonstrate poorer lineup performance compared to younger adults. Two experiments are presented which investigated the effectiveness of pre‐identification procedures aimed to reduce false identifications made by older adults. In experiment one older adults' demonstrated poorer lineup performance compared to younger adults. However, older adults benefited from pre‐lineup questions and a practice lineup prior to viewing a target absent (TA) lineup. In a second experiment, participants in the practice lineup condition made significantly fewer false identifications and more correct rejections on two TA lineups compared to participants in the control condition. On both target present (TP) lineups there was no significant difference in lineup performance between the two conditions. The effect of pre‐identification procedure on self‐reported lineup decision strategy and memory for non‐biased lineup instructions are discussed, as well as future research directions. Copyright © 2009 John Wiley &amp; Sons, Ltd.

Shifted gray encoding to reduce instruction memory address bus switching for low-power embedded systems

Gray code bus encoding is a simple approach to reduce instruction address bus switching. It requires little encoding hardware and no additional bus lines. Our analytical study reveals that with Gray encoding the address bus switching can be reduced by nearly 50%, for long, sequentially accessed code. However, existing Gray bus encoding techniques involve decoding the Gray coded bus, which is expensive in terms of performance and area, and has stymied efforts to implement such a coding scheme in real systems. Furthermore, based on our experimental investigation on a set of benchmarks, the Gray bus encoding may be much less effective than expected - the switching reduction rate can be as low as under 30%. This paper presents a design approach to enable the use of Gray encoding by avoiding the bus decoding operation and to enhance the switching reduction efficiency by using a shifted Gray code for a given application. The experiment results show that our design approach can improve bus switching reduction rate by up to 22.55%, with little overhead on design logic and performance.

Cognitive mapping through electrophysiology

Cognitive mapping through electrophysiology

CUDA-Based Radiative Transfer Method with Application to the EM Scattering from a Two-Layer Canopy Model

In step with the great efforts to find out the scattering contributions of a large number of samples in the vegetation canopy, intensive computational burden occurs and obviously lames the application of the traditional serial algorithm on the basis of the radiative transfer theory to evaluate the electromagnetic (EM) scattering from vegetations. Nevertheless, the Compute Unified Device Architecture (CUDA) gives developers access to the virtual instruction set and memory of the parallel computational elements in the CUDA compatible Graphics Processing Unit (GPU), which encourages us to develop a CUDA-based simulator for the solution. This paper analyzes the radiative transfer method and the CUDA architecture, and then presents a CUDA parallel algorithm for calculating the EM scattering from a two-layer vegetation canopy. In the CUDA-based simulation, with a GTS250 GPU as, which has 128 stream processors, coprocessor, tens of times speedup is obtained in comparison with the original serial algorithm.

Mapping Parallel FFT Algorithm onto SmartCell Coarse-Grained Reconfigurable Architecture

Fast Fourier Transform (FFT) is an important algorithm in many digital signal processing applications, and it often requires parallel implementation for high throughput. In this paper, we first present the SmartCell coarse-grained reconfigurable architecture targeted for stream processing. A SmartCell prototype integrates 64 processing elements, configurable interconnections, and dedicated instruction and data memories into a single chip, which is able to provide high performance parallel processing while maintaining post-fabrication flexibility. Subsequently, we present a parallel FFT architecture targeted for multi-core platforms computing systems. This algorithm provides an optimized data flow pattern that reduces both communication and configuration overheads. The proposed parallel FFT algorithm is then mapped onto the SmartCell prototype device. Results show that the parallel FFT implementation on SmartCell is about 14.9 and 2.7 times faster than network-on-chip (NoC) and MorphoSys implementations, respectively. SmartCell also achieves the energy efficiency gains of 2.1 and 28.9 when compared with FPGA and DSP implementations.

Remember-Know and source memory instructions can qualitatively change old-new recognition accuracy: The modality-match effect in recognition memory.

Remember-Know (RK) and source memory tasks were designed to elucidate processes underlying memory retrieval. As part of more complex judgments, both tests produce a measure of old-new recognition, which is typically treated as equivalent to that derived from a standard recognition task. The present study demonstrates, however, that recognition accuracy can be qualitatively changed by a RK or source-retrieval orientation. Visual and auditory presentations of words were varied at encoding and at test. The memory test was either a standard (old-new) recognition test, the RK test, or a source (modality) test. No effect of modality match was found on standard recognition. However, recognition accuracy in the RK and modality tests was greater when study and test modalities matched-a result obtained for both 1-step (e.g., R, K, or new?) and 2-step (e.g., old-new decision followed by RK decision for items judged old) versions of these tests. Thus, the RK and source (modality) memory procedures produced a measure of old-new recognition that was qualitatively different than standard recognition, having a greater sensitivity to perceptual information.

Design of a DI model-based Content Addressable Memory for Asynchronous Cache

This paper presents a novel approach in the design of a CAM for an asynchronous cache. The architecture of cache mainly consists of four units: control logics, content addressable memory, completion signal logic units and instruction memory. The pseudo-DCVSL is useful to make a completion signal which is a reference for handshake control. The proposed CAM is a very simple extension of the basic circuitry that makes a completion signal based on DI model. The cache has 2.75KB CAM for 8KB instruction memory. We designed and simulated the proposed asynchronous cache including CAM. The results show that the cache hit ratio is up to 95% based on pseudo ?LRU replacement policy.

P88110: A Graphical Simulator for Computer Architecture and Organization Courses

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Studying fundamental Computer Architecture and Organization topics requires a significant amount of practical work if students are to acquire a good grasp of the theoretical concepts presented in classroom lectures or textbooks. The use of simulators is commonly adopted in order to reach this objective. However, as most of the available educational simulators focus on specific topics, different laboratory assignments usually require the use of different simulators. This paper presents a graphical and interactive reduced instruction set computer (RISC) processor and memory simulator that allows active learning of some theoretical concepts covered in Computer Architecture and Organization courses. The simulator can be configured to present different processor views, from a simple serial one, without caches or pipelines, to a more realistic one with caches and superscalar execution. This approach allows a set of increasingly complex code-based laboratory assignments to be developed using a single simulator, covering topics ranging from assembly language programming to the analysis of the different kind of cache misses, pipeline hazards or branch prediction hits and misses produced during a program execution. The simulator has been included in a an automatic assessment system that helps the students to complete the assignments and helps teachers to evaluate the correctness of the students' solutions in different environments, such as high-enrollment courses or distance education. Since 1996, both the simulator and the automatic assessment system have been successfully used by more than 5000 students in Computer Architecture and Organization courses at the Technical University of Madrid (UPM), Spain. </para>

Runtime monitoring on multicores via OASES

Runtime monitoring support serves as a foundation for the important tasks of providing security, performing debugging, and improving performance of applications. Often runtime monitoring requires the maintenance of information associated with each of the application's original memory location, which is held in corresponding shadow memory locations. Unfortunately, existing robust shadow memory implementations are inefficient. In this paper, we present OASES: OS and Architectural Support for Efficient Shadow memory implementation for multicores that is also robust. A combination of operating system support (in the form of coupled allocation of memory pages used by the application and associated shadow memory pages) and architectural support (in the form of ISA support and exposed cache events) is proposed. Our page allocation policy enables fast translation of original addresses into corresponding shadow memory addresses; thus allowing implicit addressing of shadow memory. By exposing the cache events to the software, we ensure in software that the shadow memory instructions execute atomically with their corresponding original memory instructions. Our experiments show that the overheads of runtime monitoring tasks are significantly reduced in comparison to previous software implementations.

Distributed Loop Controller for Multithreading in Unithreaded ILP Architectures

Reduced energy consumption is one of the most important design goals for embedded application domains like wireless communication, multimedia and biomedical applications. The instruction memory hierarchy has been proven to be one of the most power hungry parts of the system. This paper introduces an architectural enhancement for the instruction memory to reduce energy consumption and improve performance. The proposed distributed instruction memory organization requires minimal hardware overhead and supports the execution of multiple incompatible loops in parallel in a uni-processor system. We present different methods to implement the loop controller architecture, compare them, and show that distributing the instruction memory helps to reduce the interconnect cost as well. This architecture enhancement can reduce the energy consumed in the instruction memory hierarchy by 59% and improve the performance by 22% compared to hardware based enhanced SMT based architectures.

Implementation intentions about nonfocal event-based prospective memory tasks

Implementation intentions are detailed and systematic plans that are developed during intention formation. We compared two different implementation intentions to standard event-based prospective memory instructions using three different kinds of intentions. Two of these intentions involved nonfocal cues whereas the remaining intention was about specific, focal cues. Implementation intentions dramatically increased detection performance for the nonfocal intentions. Because the exact cues could not be specified during intention formation, we argue that cue salience and that strengthening the cue to target action association are not very viable mechanisms to explain all instances of the beneficial consequences of forming implementation intentions.

Partitioning and Allocation of Scratch-Pad Memory in Priority-Based Multi-Task Systems

Energy consumption has become one of the major concerns in modern embedded systems. Recently memory subsystems have become consumed large amount of total energy in the embedded processors. This paper proposes partitioning and allocation approaches of scratch-pad memory in non-preemptive fixed-priority multi-task systems. We propose three approaches (i.e., spatial, temporal, and hybrid approaches) which enable energy efficient usage of the scratch-pad region. These approaches can reduce energy consumption of instruction memory. Each approach is formulated as an integer programming problem that simultaneously determines (1) partitioning of the scratch-pad memory space for the tasks, and (2) allocation of functions to the scratch-pad memory space for each task. Our formulations pay attention to the task periods for the purpose of energy minimization. The experimental results show up to 47% of energy reduction in the instruction memory subsystems can be achieved by the proposed approaches.

An Efficient Segmental Bus-Invert Coding Method for Instruction Memory Data Bus Switching Reduction

This paper presents a bus coding methodology for the instruction memory data bus switching reduction. Compared to the existing state-of-the-art multiway partial bus-invert (MPBI) coding which relies on data bit correlation, our approach is very effective in reducing the switching activity of the instruction data buses, since little bit correlation can be observed in the instruction data. Our experiments demonstrate that the proposed encoding can reduce up to 42% of switching activity, with an average of 30% reduction, while MPBI achieves just 17.6% reduction in switching activity.

If-conversion for embedded VLIW architectures

If-conversion refers to a compiler optimisation that eliminates conditional branches by transforming a control flow region into an equivalent set of conditional instructions. VLIW architectures, used in the design of embedded multimedia processors, can support predicated execution with a limited number of conditional instructions or a full predicated ISA. We present in this paper a speculation framework and a set of Single Static Assignment (SSA) transformations to incrementally build if-converted regions on architectures supporting the select model of conditional moves. This framework has been further extended to support a configurable set of predicated instructions and used to explore architectural variants with predicated memory instructions. We implemented this SSA if-conversion algorithm in the Open64 code generator for the ST231 processor. We show an average cycles improvement of 31% without code size penalty.

Impression‐formation advantage in memory for faces: When eyewitnesses are interested in targets' likeability, rather than their identity

AbstractThe advantage in person memory of impression formation over memory task instructions is shown to extend to the eyewitness identification paradigm. Instructions to form an impression of target persons led to more accurate identifications in subsequent photo line‐ups than explicit instructions to memorize the targets (Experiment 1). Prior knowledge that a crime was going on did not affect performance. Two confounded components of the successful instruction condition were decomposed in Experiment 2, showing that the enhanced performance is due to the impression task proper, rather than the absence of explicit memory instructions. Analyses of hits and false alarms revealed that the positive influence of impression formation on discrimination performance was due to a genuine enhancement in discrimination ability rather than merely a shift toward a stricter response criterion. Experiment 3 provided some evidence to suggest that eyewitness performance can even be influenced by recontextualization efforts and impression judgments at the time of retrieval. Copyright © 2008 John Wiley &amp; Sons, Ltd.