Insulated Field Effect Transistors Research Articles

Atomic-layer-deposited Al2O3 on Bi2Te3 for topological insulator field-effect transistors

We report dual-gate modulation of topological insulator field-effect transistors (TI FETs) made on Bi2Te3 thin flakes with integration of atomic-layer-deposited (ALD) Al2O3 high-k dielectric. Atomic force microscopy study shows that ALD Al2O3 is uniformly grown on this layer-structured channel material. Electrical characterization reveals that the right selection of ALD precursors and the related surface chemistry play a critical role in device performance of Bi2Te3 based TI FETs. We realize both top-gate and bottom-gate control on these devices, and the highest modulation rate of 76.1% is achieved by using simultaneous dual gate control.

Towards Paper Electronics – Printing Transistors on Paper in a Roll-to-Roll Process

New value-added, intelligent products with novel functionalities, e.g., sensors and simple displays have recently received much attention in the research community. For these types of products to come into everyday use, devices with reasonable electrical performance and negligible production cost are required. One way to reduce the manufacturing cost is to fabricate the electronics on inexpensive paper substrates by using roll-to-roll techniques (“Paper Electronics”), as an alternative to conventional electronics manufactured with batch processes on glass or polymer film substrates. The current work discusses printing of electronics on paper and demonstrates, as a proof-of-concept, a hygroscopic insulator field effect transistor device (HIFET) printed on paper with a custom-built roll-to-roll hybrid printer.

Competing Charge Relaxation Mechanisms in HfSiON Insulator Field Effect Transistors

We present negative bias temperature instability (NBTI) charge stress data, taken on 1 um HfSiON MOSFETs, which suggests the existence of an NBTI relaxation mechanism not previously reported in the literature. In particular, we observe significantly less NBTI damage in devices stressed in the MOSFET saturation region (large Vds) than in those stressed in the linear region (small Vds). We propose that this observation is explained by transport of trapped positive charge parallel to the channel, but inside the insulator, perhaps along a high defect density region in the HfSiON. This observation has interesting and important implications for high-k materials studies and NBTI measurement protocols.

Competing Charge Relaxation Mechanisms in HfSiON Insulator Field Effect Transistors

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Structural optimization of extremely scaled planar partially insulated field effect transistors (PiFETs)

The effects of both the separation between two partially insulated oxide layers (LPiOX) and the thickness of a partially insulated oxide layer (TPiOX) on the short channel effect (SCE) and the intrinsic propagation delay in partially insulated field-effect transistors (PiFETs) are investigated by using technology computer-aided design (TCAD) device simulation. The reverse SCE can be suppressed by controlling the tilt angle of halo implantation to Ttilt = 55°. In the case of a PiFET with the channel length (Lg), as LPiOX/Lg decreases, the subthreshold swing becomes smaller while the drain-induced barrier lowering does larger. The LPiOX/Lg and TPiOX dependence of the intrinsic propagation delay results from the variation of the junction capacitance (Cj). Cj is more sensitive to TPiOX rather than LPiOX/Lg. Conclusive optimal conditions for both SCE and the intrinsic propagation delay are summarized as LPiOX/Lg = 0.6–0.65, TPiOX ⩾ 60 nm and Ttilt = 55°, respectively.

A multilayer coated fiber-based substrate suitable for printed functionality

A recyclable multilayer coated fiber-based substrate combining sufficient barrier and printability properties for printed functional devices was developed using reel-to-reel techniques. The substrate consists of a mineral pigment layer coated on top of a barrier latex layer. The pigment layer allows controlled absorption of ink solvents. By adjusting the thickness and porosity of the top coating the printability can be tuned for various functional inks. As a proof of concept a hygroscopic insulator field effect transistor (HIFET) was successfully printed on the multilayer-coated paper.

Trapped charge dynamics in a sol–gel basedTiO2 high-k gate dielectric silicon metal–oxide–semiconductor field effect transistor

We have studied the response of a sol–gel basedTiO2, highk dielectric field effect transistor structure to microwave radiation. Under fixed biasconditions the transistor shows frequency dependent current fluctuations when exposed tocontinuous wave microwave radiation. Some of these fluctuations take the form of highQ resonances. The time dependent characteristics of these responseswere studied by modulating the microwaves with a pulse signal. Themeasurements show that there is a shift in the centre frequency of these highQ resonances when the pulse time is varied. The measured lifetime of these resonances is highenough to be useful for non-classical information processing.

Characterization of a sol-gel based high-k dielectric field effect transistor for cryogenic operation

A silicon on insulator field effect transistor for cryogenic operation has been fabricated using a sol-gel derived TiO2 electron beam resist as a high-k gate dielectric and characterized over a range of temperatures. The TiO2 dielectric layer allows too large a gate leakage current for good device operation at room temperature, but the leakage current is strongly suppressed at cryogenic temperatures and good transistor characteristics were observed. The temperature dependence of the gate leakage current suggests that Frenkel-Poole and trap-assisted tunneling dominates the conduction in the dielectric layer. The drain current shows peaks at certain frequencies under continuous wave microwave irradiation, which may be caused by the resonance of electrons trapped in defects at the TiO2/SiO2 interface. These resonances offer the possibility to manipulate single electrons for nonclassical information processing.

Performance Metrics of a 5 nm, Planar, Top Gate, Carbon Nanotube on Insulator (COI) Transistor

The performance of a planar, 5 nm top gate, carbon nanotube on insulator (COI) field-effect transistor (COIFET) with source/drain underlaps is analyzed. The performance metrics of switching delay time and cutoff frequency are calculated. A 2 nm thick, relatively low-K, SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate dielectric combined with a source/drain underlap geometry and insulating substrate minimizes the parasitic gate to source C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> and gate to drain C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> capacitances and results in a 23 fs switching delay time. The simplicity of the device design is required to satisfy the constraints of a self-assembly process. The device analyzed is also a scaled version of recently demonstrated CNTFETs on sapphire

Performance and potential of germanium on insulator field-effect transistors

The performance of field-effect transistors may be improved by increasing the channel mobility. Strained Si can accomplish this but Ge is another option. Here we show data for germanium-on-insulator (GOI) devices and also describe the simple bonding process which was used in the device fabrication. The GOI devices show better mobilities than their Si counterparts. We also show data for some metal-gate/high-κ dielectric devices on a GOI layer fabricated on a processed Si wafer. Here the GOI structure and processing does not alter the underlying Si devices and yet gives devices whose mobilities exceed those of Si devices. Simulations support the view that the improved performance results from the mobility enhancement and that the performance should also hold for submicron devices.

Applications of an all-polymer solution-processed high-performance, transistor

Low cost production and a simple manufacturing process are desired for organic field effect transistors, OFETs, even though this usually significantly lowers device performance. We report on applications and characterization of a high performance polymer field effect transistor that utilizes a hygroscopic insulator. The latter enables the device to be used as a sensor element to detect the presence of various solvents. We show a drastic change in conductivity and current modulation for some organic solvents. Furthermore, the use of the device in electric circuits is demonstrated by combining hygroscopic insulator field effect transistor (HIFET) devices in an inverter/amplifier circuit.

Operating principle of polymer insulator organic thin-film transistors exposed to moisture

The operating principle of a hygroscopic insulator field-effect transistor has been investigated. The semiconductor poly(3-hexylthiophene) shows an increased conductivity after applying the poly(vinylphenol) (PVP) insulator, which is attributed to an interfacial dipole layer caused by the permanent dipole moment in PVP. The effects of solvents on the transistor device indicate that low molecular weight protic solvents such as water, methanol, and ethanol affect the I-V characteristics significantly, in contrast to 1-propanol and aprotic solvents such as acetonitrile. The presence of a protic solvent inside the device insulator gives rise to an ion-assisted modulation of the transistor source-drain current.

A Partially Insulated Field-Effect Transistor (PiFET) as a Candidate for Scaled Transistors

Highly manufacturable partially insulated field-effect transistors (PiFETs) were fabricated by using Si-SiGe epitaxial growth and selective SiGe etch process. Owing to these technologies, pseudo-silicon-on-insulator (SOI) structures, partially insulating oxide (PiOX) under source/drain (PUSD) and PiOX under channel (PUC), could be easily realized with excellent structural and process advantages. We are demonstrating their preliminary characteristics and properties. Especially, in the PUSD PiFET, junction capacitance, leakage current, and DIBL in bulk devices could be reduced and the floating body problem in SOI devices was also cleared without any area penalty. Thus, this PiFET structure can be a promising candidate for the future DRAM cell transistor.

Use of amorphous carbon as a gate insulator for GaAs and related compounds

Deposition of gate insulator in the arsenic-based compound semiconductors (such as GaAs, AlGaAs), always causes stoichiometric changes in these materials. The deposition of any materials above 350 °C results in the segregation of As at the surface of the semiconductor, which deteriorates the metal–insulator field effect transistor properties. a-C:H can be deposited at room temperature and hence the effect of temperature on arsenic segregation can be eliminated. This work investigates the use of a-C:H as a gate insulator in arsenic-based compound semiconductors.

Field effect transistors with SrTiO3 gate dielectric on Si

SrTiO 3 has been grown epitaxially by molecular beam epitaxy on Si. The capacitance of this 110 Å dielectric film is electrically equivalent to less than 10 Å of SiO2. This structure has been used to make capacitors and metal oxide semiconductor field effect transistors. The interface trap density between the SrTiO3 and the Si is 6.4×1010 states/cm2 eV and the inversion layer mobility is 221 and 62 cm2/V s for n- and p-channel devices, respectively. The gate leakage in these devices is two orders of magnitude smaller than a similar SiO2 gate dielectric field effect transistor.

AlN and AlGaN growth using low-pressure metalorganic chemical vapor deposition

In AlGaN growth using low-pressure metalorganic chemical vapor deposition the TMA-flow-rate dependence and reactor-pressure dependence on the Al content were investigated. We found that the reduction of partial pressure of TMA is effective in preventing the reduction of the Al content. To apply AlN and AlGaN films to devices, we fabricated an insulated gate heterostructure field effect transistor (IG-HFET). The AFM image of 4 nm-thick AlN on GaN shows a rough surface composed of approximately 500 nm-size grains. The grain boundary may be the origin of the leakage current between gate and drain during the operation of the IG-HFET. Nevertheless, the device can operate with transconductance g m of 235 mS mm −1 for L g=1.4 μm.

GaAs metal insulator field effect transistors with excellent intrinsic transconductance and stable drain currents using (NH/sub 4/)/sub 2/Sx chemical treatment

Metal insulator semiconductor field effect transistors (MISFETs) and MIS capacitors are fabricated using Al metal-gate and PECVD silicon nitride (Si/sub 3/N/sub 4/) gate-insulator on commercial GaAs epitaxial wafers after treating the channel regions with (NH/sub 4/)/sub 2/S/sub x/. It is shown that the post metallization annealing (PMA) of these devices improves the transconductance and reduces the interface state density (D/sub it/) considerably. This is attributed to the additional passivation effect of hydrogen diffusing to the interface from the Si/sub 3/N/sub 4/ during the PMA. An intrinsic transconductance of 30.7 mS/mm which is 75% of the theoretical maximum limit of 40.5 mS/mm has been achieved using silicon nitride gate insulator thickness of 1100 /spl Aring/. Stability of the drain currents in these devices is demonstrated to be excellent.

Memory window of Pt/SrBi2Ta2O9/CeO2/SiO2/Si structure for metal ferroelectric insulator semiconductor field effect transistor

We have proposed a Pt/SrBi2Ta2O9/CeO2/SiO2/Si structure for a ferroelectric gate of metal ferroelectric insulator field effect transistor. A memory window of the proposed ferroelectric gate increases as electric field applied to the SrBi2Ta2O9 layer increases, and the memory window of Pt/SrBi2Ta2O9/CeO2/SiO2/Si is relatively greater than that of Pt/SrBi2Ta2O9/SiO2/Si. As a result, the Pt/SrBi2Ta2O9(140 nm)/CeO2(25 nm)/SiO2/Si structure has sufficiently programmable memory windows from 0.9 to 2.5 V in the low gate voltage range of 4–7 V.

The neuron-transistor junction: linking equivalent electric circuit models to microscopic descriptions

This paper deals with a detailed analysis of the junction that develops whenever a neuron is cultured directly on the top of a planar substrate microtransducer consisting of an insulated field effect transistor (FET). The equivalent circuit description for a patch of excitable membrane sealed to the insulating layer of a FET is provided. The patch is described according to the Hodgkin-Huxley model. Various ranges of capacitance and resistance values have been considered, under physico-chemical assumptions concerning the junction local microenvironment. Different recorded signals of neuronal activity have been simulated as a function of these values. The signals well reproduce the experimental data reported in the literature, thus suggesting the appropriateness of the analysis for the characterization of hybrid neuro-electronic systems.

GaN-AlxGa1−xN Heterostructures Deposition by Low Pressure Metalorganic Chemical Vapor Deposition for Metal Insulator Semiconductor Field Effect Transistor (Misfet) Devices

ABSTRACTIn this paper we report the fabrication and characterization of a metal insulator semiconductor field effect transistor (MISFET) based on single crystal GaN-AlxGa1−xN heterostructures. The device structure layers were deposited over sapphire substrate using low pressure metalorganic chemical vapor deposition. We discuss the fabrication and characterization of MISFET devices using single crystal GaN as the insulator layer. These were fabricated on isolated mesas using TiAu for the source and drain ohmic contacts and silver for the gate Schottky. For devices with a gate length of 4 μm (channel opening i.e. source to drain separation of 10 μm), a transconductance of 20 mS/mm was obtained at -1 volt gate bias. Complete pinchoff was observed for a gate potential of -15 volts. Device performance is compared to that for a GaN MESFET of identical dimensions.Due to its direct bandgap tunable from 3.4 to 6.2 eV AlxGa1−xN is an important semiconductor for devices in the ultraviolet and visible parts of the spectrum. The large bandgap, potential of heterojunction formation and the insulating nature of AlN make AlxGa1−xN an ideal material system for high performance metal semiconductor field effect transistor (MESFET) devices requiring high operation temperatures. Availability of the insulator (single crystal AlN or GaN) also makes possible the fabrication of metal insulator field effect transistor (MISFET) devices which has been an elusive goal for the GaAs based III-V materials technology.High quality single crystal GaN films have been deposited on sapphire and several other semiconductor substrates using metalorganic chemical vapor deposition (MOCVD)1,2, molecular beam epitaxy (MBE)3 and vapor phase epitaxy (VPE)4. Recently we have reported on quantum confinement5, room temperature stimulated emission6, and 2-dimensional electron gas in GaN-AlxGa1−xN heterostructures7,8. We have also deposited single crystal insulating GaN and A1N over sapphire using atomic layer epitaxy9,10 and fabricated high responsivity photoconductors11. We now report on the fabrication and characterization of FET devices using single crystal GaN-AlxGa1−xN heterostructures. This forms the basis of high temperature transistor devices based on the AlxGa1−xN material system.