Insulated Field Effect Transistors Research Articles

Tight-Binding Device Modeling of 2-D Topological Insulator Field-Effect Transistors With Gate-Induced Phase Transition

Tight-Binding Device Modeling of 2-D Topological Insulator Field-Effect Transistors With Gate-Induced Phase Transition

Configurable anti-ambipolar photoresponses for optoelectronic multi-valued logic gates

Anti-ambipolar transistors (AATs) are the leading platform for the paradigm shift from binary to multi-valued logic (MVL) circuits, increasing circuit integration density and data processing capacity. However, most AATs with p–n heterojunctions present limited controllability of the transconductance peak, which is key to MVL operation. Here, we report optically configurable AAT/bi-AAT photoresponses implemented with an InSe field-effect transistor for potential MVL operations. The charge trapping and detrapping processes incorporated with manually introduced trap states form the AAT peaks. Furthermore, leveraging a symmetric device configuration, the dark current is significantly suppressed, and AAT photoresponses are highlighted. Contributed by two pathways of trap states, the AAT/bi-AAT photoresponses are switchable by incident optical wavelength. This dependence facilitates optical wavelength to be one of the logic inputs for MVL, based on which we propose circuit-free ternary logic gates in a single device that can achieve more than ∼6 and ∼19 times improved data density (1 bit per transistor) for NMAX and XNOR, compared with such circuits in a traditional binary design. This work realizes optically controlled AAT photoresponses, paving the way to exploit optical wavelength as a new degree of freedom in MVL computing, offering a route toward ultra-high-density, ultra-low-power, and optically programmable optoelectronic integrated circuits.

Steep subthreshold slope “Dual-gate PN-body tied SOI-FET” – First fabrication results –

In this study, we report the first fabrication results of the steep subthreshold slope new type “dual-gate PN-body tied silicon on insulator field effect transistor (DG PNBT SOI-FET).” It simultaneously shows no hysteresis and a big Ion/Ioff ratio and also resolves the small leakage current during turn-off, which is one of the problems on “PNBT SOI-FET,” we have already reported many data on it. The results indicate that DG PNBT SOI-FET will be the more suitable candidate for the steep slope device for future ultra-low power Internet-of-things (IoT) applications.

Ballistic two-dimensional InSe transistors.

The International Roadmap for Devices and Systems (IRDS) forecasts that, for silicon-based metal-oxide-semiconductor (MOS) field-effect transistors (FETs), the scaling of the gate length will stop at 12 nm and the ultimate supply voltage will not decrease to less than 0.6 V (ref. 1). This defines the final integration density and power consumption at the end of the scaling process for silicon-based chips. In recent years, two-dimensional (2D) layered semiconductors with atom-scale thicknesses have been explored as potential channel materials to support further miniaturization and integrated electronics. However, so far, no 2D semiconductor-based FETs have exhibited performances that can surpass state-of-the-art silicon FETs. Here we report a FET with 2D indium selenide (InSe) with high thermal velocity as channel material that operates at 0.5 V and achieves record high transconductance of 6 mS μm-1 and a room-temperature ballistic ratio in the saturation region of 83%, surpassing those of any reported silicon FETs. An yttrium-doping-induced phase-transition method is developed for making ohmic contacts with InSe and the InSe FET is scaled down to 10 nm in channel length. Our InSe FETs can effectively suppress short-channel effects with a low subthreshold swing (SS) of 75 mV per decade and drain-induced barrier lowering (DIBL) of 22 mV V-1. Furthermore, low contact resistance of 62 Ω μm is reliably extracted in 10-nm ballistic InSe FETs, leading to a smaller intrinsic delay and much lower energy-delay product (EDP) than the predicted silicon limit.

The Impact of Electron Phonon Scattering, Finite Size and Lateral Electric Field on Transport Properties of Topological Insulators: A First Principles Quantum Transport Study.

We study, using non-equilibrium Green's function simulations combined with first-principles density functional theory, the edge-state transport in two-dimensional topological insulators. We explore the impact of electron-phonon coupling on carrier transport through the protected states of two widely known topological insulators with different bulk gaps, namely stanene and bismuthene. We observe that the transport in a topological insulator with a small bulk gap (such as stanene) can be heavily affected by electron-phonon scattering, as the bulk states broaden into the bulk gap. In bismuthene with a larger bulk gap, however, a significantly higher immunity to electron-phonon scattering is observed. To mitigate the negative effects of a small bulk gap, finite-size effects are studied in stanene ribbons. The bulk gap increases in ultra-narrow stanene ribbons, but the transport results revealed no improvement in the dissipative case, as the states in the enlarged bulk gaps aren't sufficiently localized. To investigate an application, we also used topological insulator ribbons as a material for field-effect transistors with side gates imposing a lateral electric field. Our results demonstrate that the lateral electric field could offer another avenue to manipulate the edge states and even open a gap in stanene ribbons, leading to an ION/IOFF of 28 in the ballistic case. These results shed light on the opportunities and challenges in the design of topological insulator field-effect transistors.

The impact of electron phonon scattering on transport properties of topological insulators: A first principles quantum transport study

Using first-principles calculations and non-equilibrium Green’s function, we study the topologically-protected carrier transport in the edges of topological insulator ribbons. We investigate the effects of electron–phonon interactions on the edge state transport. We observed that in topological insulator with small bulk gaps, electron–phonon scattering results in the bulk states broadening into the bulk gap. This leads to the destruction of the dissipationless transport. However, if the transport is restricted to the protected states, a higher immunity to electron–phonon scattering can be achieved. This can lead to the design of topological insulator field effect transistors operating based on scattering modulation, benefiting from a channel material with strong electron–phonon coupling.

Quantum Hall effect in a two-dimensional semiconductor with large spin-orbit coupling

We perform magnetotransport studies of atomically thin InSe field-effect transistors with large Rashba spin-orbit coupling (SOC), and extract the Landau level (LL) gaps via thermal activation measurements. Surprisingly, the Landau level gaps at even and odd filling factors are extrapolated to have positive and negative intercepts at $B=0$, respectively, which result from the spin-split Landau spectrum. We also show that for a material with large spin-orbit coupling, its LL gaps may vary nonlinearly and nonmonotonically as a function of magnetic field. Thus, its effective mass and $g$-factor cannot be reliably extracted using conventional expressions, but depend rather sensitively on the SOC's strength and tunability.

Phase Modulation of Self-Gating in Ionic Liquid-Functionalized InSe Field-Effect Transistors.

Understanding the Coulomb interactions between two-dimensional (2D) materials and adjacent ions/impurities is essential to realizing 2D material-based hybrid devices. Electrostatic gating via ionic liquids (ILs) has been employed to study the properties of 2D materials. However, the intrinsic interactions between 2D materials and ILs are rarely addressed. This work studies the intersystem Coulomb interactions in IL-functionalized InSe field-effect transistors by displacement current measurements. We uncover a strong self-gating effect that yields a 50-fold enhancement in interfacial capacitance, reaching 550 nF/cm2 in the maximum. Moreover, we reveal the IL-phase-dependent transport characteristics, including the channel current, carrier mobility, and density, substantiating the self-gating at the InSe/IL interface. The dominance of self-gating in the rubber phase is attributed to the correlation between the intra- and intersystem Coulomb interactions, further confirmed by Raman spectroscopy. This study provides insights into the capacitive coupling at the InSe/IL interface, paving the way to developing liquid/2D material hybrid devices.

Ion Sensitivity of Hygroscopic Insulator Field Effect Transistors

Given the many and varied roles of ions in living organisms, biocompatible organic ion sensors are a matter of considerable interest. In this work, simple, low-voltage, solid-state hygroscopic insulator field effect transistors (HIFETs) have been tested to characterise their ion-sensitive properties. Two biologically relevant salt solutions, sodium chloride (NaCl) and potassium chloride (KCl), were tested. To assess pH sensitivity, solutions of hydrochloric acid (HCl) and sodium hydroxide (NaOH) were also tested. The salts and acidic solutions caused similar, concentration-dependent changes in HIFET performance from 10 mM to 1 M, consistent with an increase in ion concentration in the hygroscopic insulator, increasing device capacitance. By contrast, basic solutions caused an overall decrease in device performance, consistent with a net removal of ions due to acid-base reactions between the insulator and the analyte. These results show that HIFETs exhibit promising sensitivity to a range of ions, and can therefore serve as platforms for future ion-selective devices.

Insight into OTFT Sensors Using Confocal Fluorescence Microscopy.

Confocal fluorescence microscopy provides a means to map charge carrier density within the semiconductor layer in an active organic thin film transistor (OTFT). This method exploits the inverse relationship between charge carrier density and photoluminescence (PL) intensity in OTFTs, originating from exciton quenching following exciton-charge energy transfer. This work demonstrates that confocal microscopy can be a simple yet effective approach to gain insight into doping and de-doping processes in OTFT sensors. Specifically, the mechanisms of hydrogen peroxide sensitivity are studied in low-voltage hygroscopic insulator field effect transistors (HIFETs). While the sensitivity of HIFETs to hydrogen peroxide is well known, the underlying mechanisms remain poorly understood. Using confocal microscopy, new light is shed on these mechanisms. Two distinct doping processes are discerned: one that occurs throughout the semiconductor film, independent of applied voltages; and a stronger doping effect occurring near the source electrode, when acting as an anode with respect to a negatively polarized drain electrode. These insights offer important guidance to future studies and the optimization of HIFET-based sensors. More importantly, the methods reported here are broadly applicable to the study of a range of OTFT-based sensors. This work demonstrates that confocal microscopy can be an effective research tool in this field.

PEDOT:PSS hydrogel gate electrodes for OTFT sensors

PEDOT:PSS hydrogel is used as soft, conductive gate electrodes for low-voltage hygroscopic insulator field effect transistors (HIFETs). HIFETs are sensitive to aqueous solutions of KCl, NaCl and H2O2, introduced through the hydrogel gate electrode.

Detection of H2O2 with Hygroscopic Insulator Organic Thin Film Transistor

AbstractHygroscopic insulator field effect transistors (HIFETs) are a class of solid‐state, low‐voltage organic thin film transistors with promising sensitivity to hydrogen peroxide (H2O2). While work has progressed on the development and understanding of HIFET‐based sensors, important questions regarding the fundamental H2O2 sensing mechanisms need to be fully investigated. In this work, a detailed study of the effects of H2O2 on the transient drain currents and transfer characteristics of HIFETs, while varying analyte concentrations and device voltages, is presented. The sensing mechanism is found to be consistent with the direct oxidation of the organic semiconductor channel, poly(3‐hexylthiophene‐2,5‐diyl), by H2O2 diffused into the device through the permeable top gate electrode and hygroscopic insulator. Further, the importance of having a transistor structure in sensing H2O2, as compared to a two‐terminal device, is demonstrated. These results represent important progress in the understanding of HIFET‐based sensors, revealing paths for future applications and optimization.

Compact Modeling of Temperature Effects in FDSOI and FinFET Devices Down to Cryogenic Temperatures

We present compact models that capture published cryogenic temperature effects on silicon carrier mobility and velocity saturation, as well as fully depleted silicon on insulator (FDSOI) and fin field effect transistor (FinFET) devices characteristics within the industry-standard Berkeley short-channel IGFET model (BSIM) framework for cryogenic IC applications such as quantum computing. For the core model charge density/surface potential calculation, we introduce an effective temperature formulation to capture the effects of the band tail states. We also present a compact model that corrects the low-temperature threshold voltage for the band-tail states, Fermi–Dirac statistics, and interface traps. New temperature-dependent mobility and velocity saturation models are accurate down to cryogenic temperature. In addition, we propose that experimentally observed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{D}$ </tex-math></inline-formula> dependence of subthreshold swing (SS) at cryogenic temperatures is a consequence of the expectedly higher rate of Coulomb scattering of free carriers.

Investigation of capacitor-less integrate and fire neuron by using dual-gate a PN-body tied silicon on insulator field-effect transistor

In this study, integrate and fire neuron by using a dual-gate (DG) PN-body tied (PNBT) silicon on insulator field-effect transistor (SOI-FET) was investigated. We found out that the DG PNBT SOI-FET has the integrate and fire function in a single device. The floating body and the positive feedback effect can perform the functions of the capacitor and comparator, respectively. The device can generate a continuous spike and also a single spike signal with the additional reset scheme. The reset action requires a recovery time, which can be controlled by voltage conditions. It has a chance of making a refractory period function. These characteristics mean that it is possible to realize the capacitor-less small footprint neuron circuit with the DG PNBT SOI-FET.

A CMOS-MEMS Accelerometer With U-Channel Suspended Gate SOI FET

There have always been demands for the development of microscale sensors with integrated miniature electronics circuitry. Requirement of external amplification for the conventional MEMS accelerometer poses limitation on scaling, design, fabrication and on-chip Integrated Circuit (IC) compatibility. These limitations could be surpassed by the implementation of integrated CMOS-MEMS architectures for sensors and actuators. Here a novel U-channel suspended gate silicon on insulator field effect transistor (USG-SOIFET) is proposed to circumvent the pseudo short channel effects (P-SCE) present in the suspended gate field effect transistor (SGFET). In the proposed USG-SOIFET, the source and drain are separated by an air-gap and thereby ensuring effective screening of drain electric field penetration into source region. The gate length (L) of USG-SOIFET is 4 times lower than the conventional planar channel SGFET for the same performance of the device. Since the same performance is achieved with a smaller length, this results in a smaller device. Finite Element Modeling (FEM) of USG-SOIFET z-axis accelerometer using CoventerMP1.3 and TCAD process, device modeling and simulation of the USG-SOIFET using Synopsys Sentaurus are presented here. The sensitivity of the accelerometer is 4.185 μA/g with a non-linearity of 4.96% for ± 5 g detection range. The bandwidth of the accelerometer is 100 Hz and the cross-axis sensitivity is found to be 3.52%. A fabrication process integration scheme for realizing USG-SOIFET has also been discussed along with process simulation to demonstrate the feasibility of realizing this new device architecture. This device platform is a potential candidate for monolithic integration with CMOS.

Stable crosslinked gate electrodes for hygroscopic insulator OTFT sensors

We report methods for fabricating stable PEDOT:PSS gate electrodes for hygroscopic insulator field effect transistors for sensing applications. Crosslinkers DVS and GOPS are used, and the challenges and advantages of each are demonstrated.

Large-area optoelectronic-grade InSe thin films via controlled phase evolution

Indium monoselenide (InSe) is an emerging two-dimensional semiconductor with superlative electrical and optical properties whose full potential for high-performance electronics and optoelectronics has been limited by the lack of reliable large-area thin-film synthesis methods. The difficulty in InSe synthesis lies in the complexity of the indium-selenium phase diagram and inadequate understanding of how this complexity is manifested in the growth of thin films. Herein, we present a systematic method for synthesizing InSe thin films by pulsed laser deposition followed by vacuum thermal annealing. The controlled phase evolution of the annealed InSe thin films is elucidated using a comprehensive set of in situ and ex situ characterization techniques. The annealing temperature is identified as the key parameter in controlling phase evolution with pure thin films of InSe developed within a window of 325 °C to 425 °C. To exert finer stoichiometric control over the as-deposited InSe thin film, a co-deposition scheme utilizing InSe and In2Se3 pulsed laser deposition targets is employed to mitigate the effects of mass loss during annealing, ultimately resulting in the synthesis of centimeter-scale, thickness-tunable ε-InSe thin films with high crystallinity. The optimized InSe thin films possess a strong optoelectronic response, exhibited by phototransistors with high responsivities up to 103 A/W. Additionally, enhancement-mode InSe field-effect transistors are fabricated over large areas with device yields exceeding 90% and high on/off current modulation greater than 104, realizing a degree of electronic uniformity previously unattained in InSe thin-film synthesis.

Energy-efficient data retention in D flip-flops using STT-MTJ

PurposeEmerging event-driven applications such as the internet-of-things requires an ultra-low power operation to prolong battery life. Shutting down non-functional block during standby mode is an efficient way to save power. However, it results in a loss of system state, and a considerable amount of energy is required to restore the system state. Conventional state retentive flip-flops have an “Always ON” circuitry, which results in large leakage power consumption, especially during long standby periods. Therefore, this paper aims to explore the emerging non-volatile memory element spin transfer torque-magnetic tunnel junction (STT-MTJ) as one the prospective candidate to obtain a low-power solution to state retention.Design/methodology/approachThe conventional D flip-flop is modified by using STT-MTJ to incorporate non-volatility in slave latch. Two novel designs are proposed in this paper, which can store the data of a flip-flip into the MTJs before power off and restores after power on to resume the operation from pre-standby state.FindingsA comparison of the proposed design with the conventional state retentive flip-flop shows 100 per cent reduction in leakage power during standby mode with 66-69 per cent active power and 55-64 per cent delay overhead. Also, a comparison with existing MTJ-based non-volatile flip-flop shows a reduction in energy consumption and area overhead. Furthermore, use of a fully depleted-silicon on insulator and fin field-effect transistor substituting a complementary metal oxide semiconductor results in 70-80 per cent reduction in the total power consumption.Originality/valueTwo novel state-retentive D flip-flops using STT-MTJ are proposed in this paper, which aims to obtain zero leakage power during standby mode.

Oxidation-boosted charge trapping in ultra-sensitive van der Waals materials for artificial synaptic features

Exploitation of the oxidation behaviour in an environmentally sensitive semiconductor is significant to modulate its electronic properties and develop unique applications. Here, we demonstrate a native oxidation-inspired InSe field-effect transistor as an artificial synapse in device level that benefits from the boosted charge trapping under ambient conditions. A thin InOx layer is confirmed under the InSe channel, which can serve as an effective charge trapping layer for information storage. The dynamic characteristic measurement is further performed to reveal the corresponding uniform charge trapping and releasing process, which coincides with its surface-effect-governed carrier fluctuations. As a result, the oxide-decorated InSe device exhibits nonvolatile memory characteristics with flexible programming/erasing operations. Furthermore, an InSe-based artificial synapse is implemented to emulate the essential synaptic functions. The pattern recognition capability of the designed artificial neural network is believed to provide an excellent paradigm for ultra-sensitive van der Waals materials to develop electric-modulated neuromorphic computation architectures.

Lattice vibration characteristics in layered InSe films and the electronic behavior of field-effect transistors

Understanding how temperature affects the structural and electronic properties for two-dimensional (2D) semiconductors could promote the application and development of nanoelectronic devices. Here, the temperature dependence of lattice structure for indium selenide (InSe) nanosheets and the corresponding electronic properties of 3 nm indium-deposited InSe field-effect transistors (FETs) are systematically demonstrated. Analyses of Raman spectra suggest that the difference of phonon frequency (Δω) for the A mode is found to be 3.14 cm−1, which is larger than that of the E mode due to the stronger electron-phonon coupling for the A mode. The device performance based on indium-deposited InSe is systematically explained using Kelvin probe force microscopy (KPFM) and the predicted energy band structure. Furthermore, FETs based on temperature and variable thickness InSe flakes are designed as applicable devices. Our findings are of fundamental importance to explain the underlying physics in intrinsic InSe transistors and improve further applications.