Input Rise Time Research Articles

Enhanced Response Time of Electrowetting Lenses with Shaped Input Voltage Functions.

Adaptive optical lenses based on the electrowetting principle are being rapidly implemented in many applications, such as microscopy, remote sensing, displays, and optical communication. To characterize the response of these electrowetting lenses, the dependence upon direct current (DC) driving voltage functions was investigated in a low-viscosity liquid system. Cylindrical lenses with inner diameters of 2.45 and 3.95 mm were used to characterize the dynamic behavior of the liquids under DC voltage electrowetting actuation. With the increase of the rise time of the input exponential driving voltage, the originally underdamped system response can be damped, enabling a smooth response from the lens. We experimentally determined the optimal rise times for the fastest response from the lenses. We have also performed numerical simulations of the lens actuation with input exponential driving voltage to understand the variation in the dynamics of the liquid-liquid interface with various input rise times. We further enhanced the response time of the devices by shaping the input voltage function with multiple exponential rise times. For the 3.95 mm inner diameter lens, we achieved a response time improvement of 29% when compared to the fastest response obtained using single-exponential driving voltage. The technique shows great promise for applications that require fast response times.

Statistical Analysis for Pattern-Dependent Simultaneous Switching Outputs (SSO) of Parallel Single-Ended Buffers

Switching currents of simultaneous switching output (SSO) buffers can cause significant power-supply-induced jitter (PSIJ) and uncertainty in the output voltages. The bit error rate (BER) can be simulated by considering all possible input data patterns with a long data sequence; however, it requires large computational efforts. In this paper, the SSO waveforms are analytically calculated, including the rise time of the input voltage, and the probability density functions (PDFs) of the waveforms are analytically calculated. The PDFs of the SSO step responses are combined with the inter-symbol interference (ISI) PDF extraction. The statistical eye and BER eye diagrams obtained from the proposed method are validated with HSPICE simulations. The effects of the SSO patterns as well as the channel ISI are successfully included in the proposed method. Also, the effects of input rise time and the number of parallel SSO buffers are investigated, and the proposed method is extended for analysis of SSO buffers with the data bus inversion (DBI) coding. The method should be practically useful for design of wideband memory I/O interfaces and low-cost consumer devices by reducing the computational time of the jitter and BER drastically.

Signal delay effects of solid dielectrics on time-of-flight measurements in GIS

So-called ‘time-of-flight’ (TOF) measurements have been employed for locating PD sources within GIS for over 20 years. Portable digital sampling oscilloscopes have now become available for reasonable cost whose input rise-times, bandwidths, and sampling rates are theoretically sufficient to provide spatial resolution within approximately 10 centimeters. However, contrary to first impressions, GIS does not present an ideal propagation environment for GHz bandwidth radio frequency (RF) signals; many factors act to prevent reaching such high spatial resolution. In both laboratory measurements and field simulations, the authors have recently observed that solid dielectric insulators in the signal propagation path affect the accuracy of the location determination. Therefore, it is important to take the delay effects of solid dielectrics into account in order to increase accuracy of TOF measurements. To this end, comparison measurements were made on a short section of GIS which clearly demonstrate the delay time effects as UHF signal pass through solid insulators. In addition, a sophisticated finite elements (FE) RF model was created for the same section of GIS in order to simulate electromagnetic wave propagation within it. The simulation results obtained were compared against the measurements for validation purposes. In addition, results from a practical on-site measurement are presented along with suggestions for others working in the field.

Compact modeling of response time and random-dopant-fluctuation-induced variability in nanoscale CMOS inverter

As MOSFETs are scaled down to nanometer feature size, random dopant fluctuation (RDF) severely affects CMOS digital integrated circuits (ICs). This paper proposes compact models for estimation of response time and RDF-induced variability in nanoscale CMOS inverter by solution of differential equation considering both input rise time and gate–drain coupling capacitance. The timing characteristics, including propagation delay, overshooting time and transition time, as well as its variability, are accurately modeled in analytical expressions. The proposed models are verified with HSPICE simulations. Monte Carlo analysis also confirms that the models are simple and effective in different design decisions such as width length ratios, load capacitances and source voltages. The studies show that a 7.59% spread in VT variation due to RDF results in about 5% spread in delay variability for the 65nm CMOS inverter.

Analysis and Modeling of Energy Consumption in RLC Tree Circuits

In this paper, the energy consumption of resistance-inductance-capacitance ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RLC</i> ) trees is analytically modeled. In particular, the results obtained by the same authors for <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> tree circuits are generalized, allowing for a deep understanding of the impact of the inductance. The modeling approach proposed relies on the adoption of an equivalent second-order <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RLC</i> circuit, whose energy consumption is evaluated in a closed form. These results are then extended to <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RLC</i> circuits with arbitrary order, deriving a simple and accurate model. The energy dependence on the input rise time is also analyzed in detail, identifying the ranges for which the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RLC</i> circuit can be approximated to a simple capacitance or an <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> circuit. The model equations provide an insight into the dependence of the energy consumption on the circuit parameters. Indeed, the energy is explicitly expressed as a function of the resistances, capacitances and inductances of the original network. The energy model proposed is shown to be accurate enough for modeling purposes through comparison with SPICE simulations, as the error is typically in the order of a few percentage points.

Closed-Form &lt;emphasis&gt;RC&lt;/emphasis&gt; and &lt;emphasis&gt;RLC&lt;/emphasis&gt; Delay Models Considering Input Rise Time

The Elmore delay model is the most popular and efficient delay model used for analytical delay estimation. Closed-form delay formulas are useful for circuit design, timing-driven physical design, synthesis, and optimization. As signal rise time becomes faster and the line resistance becomes smaller from copper technology, the significance of inductance increases. Both RC and RLC delays are a strong function of signal rise time. We propose a novel and efficient delay modeling method based on nondimensionalization to consider finite input rise time as an improvement over the Elmore's approach. To further improve the accuracy of the delay model, a new correction method, effective distance correction factor (EDCF), is proposed to consider resistive shielding of downstream capacitance. EDCF can be used to correct the delays for both RC and RLC tree structures. The proposed delay modeling method was applied to a number of nets selected from an integrated circuit (IC) design, and the delay estimation results were compared with HSPICE simulations. The new delay model retains the efficiency and simplicity of the Elmore delay model with significantly improved accuracy.

Energy consumption in RC tree circuits

In this paper, resistance-capacitance (RC) tree networks are modeled in terms of their energy consumption associated with an input transition. This work significantly extends the results that the same authors previously obtained in the specific case of ladder networks with only ramp signals. The proposed approach to model the energy consumption is based on a single-pole approximation, in which an equivalent time constant is analytically derived from an exact analysis for very slow and very fast input transitions. The model is then extended to arbitrary values of the input rise time by exploiting some intrinsic properties of RC tree networks. The approach is completely analytical and leads to closed-form results. Analytical results are explicitly derived for different inputs, such as the ramp and the exponential waveforms which are usually encountered in current VLSI circuits, as well as the saturated sine input. Due to its simplicity, the proposed energy expression is suitable for pencil-and-paper evaluation and allows for an intuitive understanding of the network dissipation. The energy expression proposed is shown to be accurate enough for modeling purposes through comparison with SPICE simulations.

Evaluation of energy consumption in RC ladder circuits driven by a ramp input

In this paper, the energy consumption of RC ladder networks, which can represent chains of transmission gate or long wire interconnections, is modeled. Their energy dependence on the input rise time is analyzed by assuming a ramp input waveform. Since the analysis can be carried out in a straightforward manner only for very simple RC ladder networks, the exact analysis is first limited to asymptotic values of the input rise time T (i.e., for T/spl rarr/0 and T/spl rarr//spl infin/). Successively, the energy expression is extended to arbitrary values of the input rise time by introducing a suitable equivalent first-order RC circuit, whose resistance and capacitance are simply related to the resistances and capacitances of the original network. The energy expression found is useful for pencil-and-paper evaluation and affords an intuitive understanding of the network dissipation, since each term has an evident physical meaning. By comparison with SPICE simulations, the energy expression proposed is showed to be accurate enough for modeling purposes.

Modelling of source‐coupled logic gates

AbstractIn this paper, the modelling of CMOS SCL gates is addressed. The topology both with and without output buffer is treated, and the noise margin as well as propagation delay performance are analytically derived, using standard BSIM3v3 model parameters.The propagation delay model of a single SCL gate is based on proper linearization of the circuit and the assumption of a single‐pole behaviour. To generalize the results obtained to cascaded gates, the effect of the input rise time and the loading effect of an SCL gate are discussed.The expressions obtained are simple enough to be used for pencil‐and‐paper evaluations and are helpful from the early design phases, as they relate SCL gates performance to design and process parameters, allowing the designer to gain an intuitive understanding of performance dependence on design parameters and technology.The model has been validated by comparison with extensive simulations using a 0.35‐µm CMOS process. The model agrees well with the simulated results, since in realistic cases the difference is less than 20% both for noise margin and delay. Therefore, the model proposed can be profitably used for pencil‐and‐paper evaluations and for computer‐based timing analysis of complex SCL circuits. Copyright © 2002 John Wiley &amp; Sons, Ltd.

Generalized Interconnect Delay Time and Crosstalk Models: II. Crosstalk-Induced Delay Time Deterioration and Worst Crosstalk Models

New analytical models for estimating crosstalk-induced delay time deterioration and the worst crosstalk models of a coupled interconnect for ramp input waveform are derived. The accuracy of these compact models at various driver resistances, loading capacitances, and input-ramping rates is verified by simulation program with integrated circuit emphasis (SPICE) simulation for the parallel interconnect system. The effects of crosstalk noise on the delay time at various ramp input rise times, for both simultaneous and non-simultaneous switching cases, are discussed here. In this study we show that crosstalk noise will be a limiting factor for future fast transition signals. The results reported herein are useful in the studies of delay time uncertainties due to noise and the interconnect worst-case design.

Interconnection channel capacity under crosstalk noise

The channel capacity of a parallel bus structure was examined in relation to the ever increasing demand for signal input and output. The limitations on signal integrity caused by both far-end and near-end crosstalk noise were considered. Expressions for the signal waveforms were developed using a rudimentary model. The expressions were then used to evaluate the channel capacity for perfectly matched lines in the high-frequency regime where skin effect and dielectric loss dominate the loss due to the static resistance. The analysis showed that binary logic yields the maximum channel capacity. For the parameters assumed as an illustrative example, the input rise time needed to achieve the maximum channel capacity cannot be achieved with today's technology. For source rise times longer than this threshold or optimum rise time, the maximum channel capacity is achieved by using multilevel logic. In the case of short lines, insufficient coupling exists between lines to meet the channel capacity condition for two levels. Therefore, for short lines multiple logic also is necessary to achieve maximum channel capacity.

A comprehensive delay model for CMOS inverters

A method to accurately calculate the delay and the output transition-time of a CMOS inverter for any input ramp and output loading is considered. This paper is an extension of Sakurai's work (1990) on delay modeling of inverters for fast input ramps. We observed that two different mechanisms, that can be adequately modeled analytically, govern the delay and the output transition-time of an inverter in two extreme cases: infinitely fast and infinitely slow inputs. These extreme points are joined by a curve that can predict the delay and the output transition-time for any input. We found that the delay and the output transition-time for an inverter with small fanouts are similar to those for large input transition-times. This behavior is explained by the use of I-V trajectories. We describe a method to generate parameters to model delay and output transition-time for different fanouts and input transition-times; this method can be generalized to add parameters for different temperatures and supply voltages. Given a new process technology and its corresponding SPICE-model parameters, our delay calculation scheme comprises characterizing a minimal number of coefficients for each new technology (a one-time process) and evaluating the analytical forms thereafter to obtain the delay and the transition-time. Our delay equations also explain negative delays that arise in case of slow input rise-times. A program incorporating the above idea has been implemented in C. Delay and transition-time values obtained from the program have been found to be typically within 3% of SPICE. >

Hot-carrier-reliability design rules for translating device degradation to CMOS digital circuit degradation

Long term ring-oscillator hot-carrier degradation data and simulation results are compared to demonstrate that a circuit reliability simulator BERT can predict CMOS digital circuit speed degradation from transistor DC stress data. Initial fast degradation is noted and attributed to the "zero crossing" effect caused by PMOSFET current enhancement. Saturation drain current, measured at V/sub gs/=V/sub ds/=Vdd/2, is a better monitor for CMOS circuit hot-carrier reliability. We present generalized hot-carrier-reliability design rules, lifetime and speed factors, that translate DC device lifetime to CMOS digital circuit lifetime. The design rules can roughly predict CMOS circuit degradation during the initial design and can aid reliability engineers to quickly estimate the overall product hot-carrier reliability. The NMOSFET and PMOSFET lifetime factors are found to obey 4/ft/sub rise/ and 10/ft/sub fall/, respectively. Typically, the NMOSFET and PMOSFET speed degradation factors are 1/4 and 1/2, respectively, with saturation region drain current as the monitor while, for a 100 MHz operating frequency and for an input rise time of 0.35 ns, the NMOSFET and PMOSFET lifetime factors are 120 and 300, respectively.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Hot-carrier-reliability design guidelines for CMOS logic circuits

Long-term ring-oscillator hot-carrier degradation data and simulation results are compared to demonstrate that a circuit reliability simulator BERT can predict CMOS digital circuit speed degradation from transistor DC stress data. We present generalized hot-carrier-reliability design rules that translate device-level degradation rate to CMOS circuit lifetime. The design rules, which consist of lifetime and speed degradation factors, can roughly predict CMOS circuit degradation during the initial design, and can help reliability engineers to quickly estimate the overall product hot-carrier reliability. The NMOSFET and PMOSFET lifetime factors were found to obey 4/ft/sub rise/ and 10/ft/sub fall/ respectively. Typically, the NMOSFET and PMOSFET speed degradation factors are 1/4 and 1/2, respectively, with saturation region drain current as the monitor, while for a 100 MHz operating frequency and for an input rise time of 0.35 ns, the NMOSFET and PMOSFET time factors are 120 and 300, respectively.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Accurate delay estimation model for lumped CMOS logic gates

Recently a novel slope delay model for timing verification in digital CMOS circuits has been presented by H.G. Yang and D.M. Holburn (see ibid vol.137, p.405-12, 1990). Three different classifications were made, based on the risetime (slope) of the input waveforms, as follows: quick-no effect of input risetime on the output voltage; intermediate-small effect of input risetime on the output delays; and slow-significant effect of input risetime on the output delays. In the analysis of the slow waveform, the input voltage to the inverter was taken as 0.5 (V/sub dd/-V/sub tn/+kt/sub 0/), because otherwise there is no analytic solution. This assumption is valid as long as the input voltage is rising. If this approximation is continued after the input voltage reaches V/sub dd/, then the current through the NMOS transistor is consistently underestimated, and the fall-time is overestimated. Hence, a more accurate representation of input waveform is necessary to obtain more reliable delay estimates.

Modeling of high-speed, large-signal transistor switching transients from s-parameter measurements

A new technique has been developed to derive the large-signal transient response of semiconductor devices from small-signal frequency response data. The large-signal switching response can be calculated for an arbitrary input signal voltage and rise time. This new technique utilizes the Fourier transformation to combine arrays of small-signal data to compute the response waveform. The input waveform is decomposed into a superposition of small pulses. The response to each pulse is obtained by Fourier transformation techniques, using s-parameter data at appropriate bias points. The sum of these responses approximates the overall transient response. Simulations were performed for a GaAs MESFET for step inputs with the rise times of 8 ns and 150 ps. Good agreement was obtained between simulated waveforms and measured output waveforms in rise time, magnitude, and waveform shape. This algorithm is general and will work for other measured small-signal transfer parameters as functions of frequency and bias.

Timing discriminator using leading-edge extrapolation

We describe a circuit which recovers the timing information inherent in a slow-rising input pulse, producing an output “timing edge” a fixed time after the starting corner of the input pulse. Output time is nearly independent of input risetime, input pulse height, and discriminator threshold setting. The circuit uses two switched current sources which charge a single capacitor. Experimental results are given for pulser-generated inputs as well as real signals from a large high-energy calorimeter.

Evaluation of the theory of cardiac-output computation from transthoracic impedance plethysmogram

To analyse the limit of the stimation of stroke volume by thoracic impedance plethysmography (SVz), we considered an elastic tube forced with a trapezoidal flow input as a model of the aorta, and, based on Kubicek's equation, the volume input (SVa) was related to its impedance change via the model system parameters such as elasticity, fiuid inertia, peripheral resistance, total impedance across the tube and the rise and fall time of the input. SVz is equal to SVa only when the inflow is a square wave. The ratio SVz/SVa decreases with increasing input rise time, while it increases with increasing fall time, if the maximum flow rate and ejection time of the inflow are held constant. SVz hardly changes in association with changes in elasticity, fluid inertia, peripheral resistance or total impedance. A part of the results, the relationship between SVz, transthoracic total impedance and aortic flow waveform, was also demonstrated in dogs.

Transient analysis of multiple-input integrated digital structures

This paper presents an insight into the transient performance and propagation delay of complex integrated multiple-input structures in relation to a large digital system, taking into account the intrinsic parameters associated with device geometry. Modeling is therefore performed at the gate level. A piecewise linear model is used for the various transient intervals and the analysis employs fixed time steps. Experimental observations give ample evidence of good agreement between the theoretical and computed results, for which various values of input rise and fall times and different values of fan-out, β <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</inf> , and f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> are used. An accurate appraisal of the storage time associated with the gate is thus possible. Detailed solutions determine the main factors that offer scope for improvement for the structure studied, and suggest means of optimizing the transient response using the derived analytical expressions.

Aspects of Resolution Degradation in a Nuclear Pulse Analyzer System

Common causes of resolution degradation are discussed for low and high count rates. Previous works have presented signal/noise versus shaping networks for Johnson noise and 1/f2 noise. Equations are derived here to include l/f noise, which is found to be significant. Results are presented for peak-height change versus input rise time for different shaping networks. For high count rates, the need for an amplifierwithlongtime constants and the use of a baseline restorer are discussed. A restorer and deadtime gating circuits are presented, along with experimental results.