Abstract
As MOSFETs are scaled down to nanometer feature size, random dopant fluctuation (RDF) severely affects CMOS digital integrated circuits (ICs). This paper proposes compact models for estimation of response time and RDF-induced variability in nanoscale CMOS inverter by solution of differential equation considering both input rise time and gate–drain coupling capacitance. The timing characteristics, including propagation delay, overshooting time and transition time, as well as its variability, are accurately modeled in analytical expressions. The proposed models are verified with HSPICE simulations. Monte Carlo analysis also confirms that the models are simple and effective in different design decisions such as width length ratios, load capacitances and source voltages. The studies show that a 7.59% spread in VT variation due to RDF results in about 5% spread in delay variability for the 65nm CMOS inverter.
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