Input Reference Frequency Research Articles

A Novel Self-Biased Phase-Locked Loop Scheme for WLAN Applications

This article presents a novel self-biased phase-locked loop (PLL) scheme for wireless local area network (WLAN) applications. A novel self-biased circuit that contains a current mirror circuit and a variable resistor circuit related to the frequency division ratio are proposed. The proposed self-biased PLL scheme achieves a fixed damping factor. Moreover, the self-biased technology allows the PLL loop bandwidth to track the input reference frequency and division ratio. The proposed start-up circuit speeds up the locking of the PLL. In addition, the proposed differential-to-single-ended (DTS) converter can guarantee a 50% duty cycle without operating the PLL at twice the chip operating frequency. The proposed self-biased PLL is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 55 nm CMOS process. The measured root-mean-square jitter (RMS-jitter) integrated of PLL is 2.4 ps with a dissipation of 8.6 mW, and the resulting figure-of-merit is −223.05 dBc/Hz.

A New Blind Zone Free PFD in Fractional-N PLL for Bluetooth Applications

This paper presents a new Phase Frequency Detector (PFD) used in the Fractional-N synthesizer PLL for the Bluetooth range frequencies using TSPC based D-FF. The PFD is designed by using 16 transistors. The operating frequency of the PFD can be modelled in between 2.2GHz-3.8GHz with an input reference frequency is applied of about 50MHz. The design of PFD is done by using GPDK 45nm CMOS technology on SPECTRE simulator with 1.8 V supply voltage. The designed PFD is having maximum operating range and free from blind zone. The results reported in this paper are compared and focused on the blind zone and minimum jitter contribution. The designed PFD consumes least power, minimum number of transistors and minimum jitter contributed by the transistors as compared with the reset free based PFD.

A Wide Dynamic Range and Low Bit Error Pixel TDC Suitable for Array Application

This brief presents a cascade pseudo 3-level time-to-digital converter (TDC) based on wideband phase-locked loops (PLLs) for photon time of flight measurement. In each pixel, a 9-bit pseudo random synchronous counter composed of linear feedback shift register is served as a high-level coarse TDC. Its counting clock is directly coming from the synchronous counter served as the middle-level TDC. The low-level fine TDC is based on time-interpolation technology and directly use the low-jitter multi-phase clock signal generated by the PLL to complete the fine quantization of the residue time. In addition, proper timing control and error suppression methods are implemented in the proposed TDC. The circuit is demonstrated in TSMC 0.35- ${\mu }\text{m}$ CMOS process. Under the condition of 10-MHz input reference frequency and 3.3-V supply voltage, the wideband PLL can be locked from 146 to 450 MHz. The resolution of the TDC will change from 856 to 278 ps. At 450 MHz, the measured DNL around $15\boldsymbol {\mu }\text{s}$ is–0.1 to 0.1 LSB and the INL is–0.05 to 0.2 LSB.

RHBD Charge Pump PLL based 2.4 GHz Frequency Synthesizer

Frequency Synthesizer forms the heart of electronic communication system. Phase Locked Loop (PLL) based Frequency Synthesizers over the years has become the ubiquitous solution for generation of stable clock source. But it is a challenging task to design and develop PLL to be used in radiation environment such as in satellites, space systems and military electronics. Since impact of radiation strike on PLL is said to introduce transient faults resulting in increased timing jitter, distortion in phase, and bit flips. One or more of the above said effects can initiate false triggering which may result in incorrect data to be latched, loss of synchronization in data processing and networking. This may lead to catastrophic effect. Hence, as the stability of frequency synthesizer is of vital importance, there is a stressful need for design of radiation hard, fault tolerant frequency synthesizer. With this motivation, in this paper, a radiation hard CMOS Charge Pump PLL is designed to synthesize a 2.4GHz frequency source using 20MHz reference input frequency. The proposed radiation hard PLL design uses a hybrid Radiation Hardening By Design (RHBD) fault tolerant technique combined with redundancy, hence offering a twofold level of fortification from radiation spikes. Cadence tool was used for simulation. The PLL designed has exhibited satisfactory performance. The RHBD Charge Pump PLL in presence of radiation strike resulted in rms jitter of 128.9ps, phase noise of -94.03dbc/Hz and settling time of 159ns against the IEEE 802.11b/g standard requirement of 250ps jitter, -110dbc/Hz phase noise and 10us setting time.

Adaptive PFD selection technique for low noise and fast PLL in multi-standard radios

Selecting the fast phase frequency detector (PFD) before the loop locks and the low noise PFD after locking, a fast and ultralow noise phase locked loop (PLL) design is achieved in this work. We propose a dual PFD architecture of a PLL which combines the benefits of both the PFDs and heavily shrinks the tradeoffs among phase noise, power consumption and lock time of the PLL. This is achieved by adaptively selecting the PFD at suitable instants of operation of the PLL. Phase noise analysis of the proposed PLL has been carried out and the results of Cadence design simulation are reported for comparison with other standard PLL architectures. The lock time of this PLL is found to be 90ns consuming an average power of 1.2mW for an input reference frequency of 1.25GHz. It also operates over a wide lock range of 0.7–2.8GHz so that it can be used in cellular handsets for multiple radio standards like GSM and WiMAX.

Design of Positive Edge Triggered D Flip-FlopUsing 32nm CMOS Technology

The usage of the low power consumptions devices in today’s global village has become pervasive and indispensable in almost every walk of life. The thrust is towards reducing the high power energy consumption, required to reduce cost of the circuitry, while increasing the speed of performances in any operations. A high speed low power consumption positive edge triggered Delayed (D) flip-flop can be design for increasing the speed of counter in Phase locked loop, using 32 nm CMOS technology. Here we design D flip-flop for Phase locked loop (PLL). Phase locked loop is an important analog circuit used in various communication applications such as frequency synthesizer, radio computer, clock generation microprocessors etc. The design counter can be used in the divider chip of the phase locked loop. A divide counter is required in the feedback loop to increase the VCO frequency above the input reference frequency. The propose circuit will faster than conventional circuit as it will have fast reset operation. The circuit will consumes less power as it prevents short circuit power consumption. The circuit operates at low voltage power supply. The CMOS based fast D flip-flop circuit can be design and simulated by using Microwind 3.1 tool.

A Low Power 0.18-μm CMOS Phase Frequency Detector for High Speed PLL

This paper presents a modified high speed CMOS dynamic phase frequency detector (PFD) for high frequency phase-locked loop (PLL). Design miniaturizations in downscaling CMOS process lead to circuit malfunction due to intrinsic effects and many other reasons. To ensure main characteristics of the PFD are preserved, the proposed dynamic PFD uses 18 transistors operated with 1.2 V power supply. The performance of the design is focused on power supply, power dissipation, wide input frequency range, dead zone size and active layout area. The circuit is designed in 0.18 μm CMOS process using Mentor Graphics environment. In this paper, the dynamic PFD dissipates 59 pW of total power when reference input frequency clock operates at 50 MHz and feedback input frequency clock operates up to 4 GHz. The dead zone has been eliminated. The simulation results show that the circuit offered an alternative for any high speed and low power PLL applications. DOI: http://dx.doi.org/10.5755/j01.eee.20.9.5312

An exact formula for the maximum VCO sweep rate of a PLL

In many phase-locked loop (PLL) applications, the natural pull-in mechanism is too slow and unreliable, and it must be accelerated. By adding an externally-generated ramp to its control voltage input, the PLL voltage controlled oscillator (VCO) frequency can be swept towards the input reference frequency in an attempt to speed up the pull-in process. This popular acquisition aid has a significant limitation when it is used in a second-order, Type II PLL. If the applied ramp voltage has a slope magnitude greater than (alternatively, less than) some value Rm, the PLL state can (alternatively, cannot) sweep past the desired lock point, resulting in a phase lock failure (alternatively, success). In general, the maximum sweep rate magnitude Rm can be computed by using a numerical integration-and-search procedure that is described in the PLL literature. A special case exists for a second-order, Type II PLL that incorporates a triangular-characteristic phase detector (with logic-level binary input signals). For this case, it is possible to develop an exact, closed-form expression for Rm, the main result of this paper. For a range of loop parameters most often used in applications, Rm values are computed by using the exact formula, and these are used in two ways. First, they are used to validate the previously-mentioned numerical integration-and-search procedure. Second, they are compared to maximum sweep rate values computed for a PLL that utilizes a sinusoidal phase detector to show that the triangular-phase-detector PLL can be swept significantly faster than the sinusoidal-phase-detector loop.

An Analytical Approximation for the Pull-Out Frequency of a PLL Employing a Sinusoidal Phase Detector

The pull-out frequency of a second-order phase lock loop (PLL) is an important parameter that quantifies the loop's ability to stay frequency locked under abrupt changes in the reference input frequency. In most cases, this must be determined numerically or approximated using asymptotic techniques, both of which require special knowledge, skills, and tools. An approximating formula is derived analytically for computing the pull-out frequency for a second-order Type II PLL that employs a sinusoidal characteristic phase detector. The pull-out frequency of such PLLs can be easily approximated to satisfactory accuracy with this formula using a modern scientific calculator.

An Analytical Approximation for the Pull-Out Frequency of a PLL Employing a Sinusoidal Phase Detector

The pull-out frequency of a second-order phase lock loop (PLL) is an important parameter that quantifies the loop's ability to stay frequency locked under abrupt changes in the reference input frequency. In most cases, this must be determined numerically or approximated using asymptotic techniques, both of which require special knowledge, skills, and tools. An approximating formula is derived analytically for computing the pull-out frequency for a second-order Type II PLL that employs a sinusoidal characteristic phase detector. The pull-out frequency of such PLLs can be easily approximated to satisfactory accuracy with this formula using a modern scientific calculator.

Performance Improvement of Digital Phase Locked Loop Algorithm Using all Pass Filter and Low Pass Filter for Grid Connected Inverter Reference

Digital Phase Locked Loop (PLL) is an algorithm that is used to detect the phase, frequency, and amplitude of a signal. The output of digital PLL algorithm can be used as synchronization reference for grid connected inverter. A digital PLL algorithm is very popular to be used since its structure is very simple and it has high accuracy. However, the output of digital PLL is not stable if the input reference frequency is shifted from the pre-defined fundamental frequency and that condition will result an oscillation in digital PLL output. In this paper, an algorithm modification is employed using low pass filter and all pass filter to improve the digital PLL output response under various condition. All simulation results will be shown and compared to the conventional algorithm.

A High-Speed, Low Power Consumption Positive Edge Triggered D Flip-Flop for High Speed Phase Frequency Detector in 180 nm CMOS Technology

A high speed low power consumption positive edge triggered Delayed (D) flip-flop was designed for increasing the speed of counter in Phase locked loop, using 180 nm CMOS technology. The designed counter has been used in the divider chip of the phase locked loop. A divide counter is required in the feedback loop to increase the VCO frequency above the input reference frequency. The proposed circuit is faster than conventional circuit as it has fast reset operation. The circuit consumes less power as it prevents short circuit power consumption. The circuit operates at 1.8V power supply. This work has been used in the design. of 2.4 GHz CMOS PLL targeting OFDM application. The CMOS based fast D-ff circuit has designed and simulated by Virtuoso tool of CADENCE spectre

An Exact Formula for the Pull-Out Frequency of a 2nd-Order Type II Phase Lock Loop

The pull-out frequency of a Phase Lock Loop (PLL) quantifies the loop's ability to remain frequency locked under abrupt changes in the reference input frequency. This parameter is very critical in many applications e.g. FSK demodulator, multicarrier, and frequency-hopping based systems. In most cases, this parameter must be determined numerically or approximated using asymptotic techniques. Either of the methods needs special knowledge, skill and tools. An exact formula is derived for computing the pull-out frequency for a 2nd-order Type II PLL that employs a triangular characteristic phase detector. With this formula, the pull-out frequency of such PLLs can easily be calculated using a current day scientific calculator.

ON THE DESIGN OF ADAPTIVE-BANDWIDTH ALL-DIGITAL PHASE-LOCKED LOOPS

The second-order adaptive-bandwidth all-digital phase-locked loop (ADB-ADPLL) is designed and analyzed by using a new design procedure. Based on a discrete-time analogy of a continuous-time PLL (CTPLL) with the z-transform, the design criterion of the ADB-ADPLL is derived and a design procedure is developed. Following the design criterion, the ADB-ADPLL can adapt its system parameters to balance the loop noise bandwidth and lock-in time. According to the design criterion, the ratio of the loop bandwidth to the reference input frequency can be maintained as a constant if the sampling frequency is a fixed multiplier of the input frequency. An example is given to illustrate the design procedure and simulation results are presented to validate the adaptive characteristics with respect to the phase noise and varying bands of input frequency.

Dynamic Linearizing Modulator for Large-signal Linearization of a Boost Converter

Various methods to linearize the control-to-output behavior of a boost converter are discussed. Most of the previously reported linearizing techniques are not suitable when the reference input amplitude or frequency is large. In this paper, a dynamic linearizing modulator for the boost converter is proposed, which transforms the open-loop converter into a linear amplifier with an operating frequency as high as one-fifth the switching frequency. The modulator generates a duty ratio by comparing the nonlinear part of the boost converter dynamic equation with a sine wave reference voltage on a cycle-to-cycle basis. The technique exhibits superior audio susceptibility due to the feedforward of input voltage. The formulation, implementation, and verification of this technique are discussed. Experimental results show the validity of the technique for a reference input frequency up to one-fifth the switching frequency.

A Low Power and Wide Range Programmable Clock Generator With a High Multiplication Factor

A programmable delay locked loop (DLL) based clock generator, providing a high multiplication factor, has been developed in a 0.18- μm CMOS technology. Utilizing the proposed pulse generator, purely consisting of D flip flops (DFFs) and inverters, the clock generator provides a high multiplication factor of up to 24. It consumes only 16.2 mW when generating 2.16 GHz output signals. In addition, the proposed saturated-type unit delay cell adopted in the voltage controlled delay line (VCDL) is capable of providing a long delay while maintaining fast-switching signal edges. Thus, the DLL can lock up an input reference frequency as low as 30 MHz while maintaining good phase noise performance and small chip area occupancy. The phase noise is -88.7 and -99.8 dBc/Hz at 10 kHz and 100 kHz offsets, respectively, from the operating frequency of 1.2 GHz, which is equivalent to a 1.7 ps RMS jitter. The active chip area takes only 0.051 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

개선된 자동 주파수 보정회로를 이용한 광대역 클록 발생기 설계

In this paper, a wideband clock generator using novel Automatic frequency calibration(AFC) scheme is proposed. Wideband clock generator using AFC has the advantage of small VCO gain and wide frequency band. The conventional AFC compares whether the feedback frequency is faster or slower then the reference frequency. However, the proposed AFC can detect frequency difference between reference frequency with feedback frequency. So it can be reduced an operation time than conventional methods AFC. Conventional AFC goes to the initial code if the frequency step changed. This AFC, on the other hand, can a prior state code so it can approach a fast operation. In simulation results, the proposed clock generator is designed for DisplayPort using the CMOS ring-VCO. The VCO tuning range is 350㎒, and a VCO frequency is 270㎒. The lock time of clock generator is less then 3us at input reference frequency, 67.5㎒. The phase noise is -109dBC/Hz at 1MHz offset from the center frequency. and power consumption is 10.1㎽ at 1.8V supply and layout area is 0.384㎟.

A 50.8–53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13-$\mu$m CMOS

A 50.8-53-GHz clock generator with a quadruplicate-harmonic-locked phase detector (PD) is presented to achieve a low spur and a low reference frequency. The proposed quadruplicate-harmonic-locked PD, a low-voltage Colpitts voltage-controlled oscillator, and a wide-range divide-by-2 divider are also presented. This clock generator has been fabricated in a 0.13-mum process. The measured reference spur is -59.88 dBc at 51.02 GHz with an input reference frequency of 199.3 MHz. The area is 0.93 mm times 1 mm with the on-chip loop filter and pads. It dissipates 87 mW without buffers from a 1.5-V supply.

Precise motion control of a nanopositioning PZT microstage using integrated capacitive displacement sensors

We propose a hysteresis and drift compensation scheme using proportional-integral feedback control for a nanopositioning Pb(ZrTi)O3 (PZT) microstage. A multi-degree of freedom PZT microstage with integrated differential capacitive displacement sensors has been fabricated and tested, demonstrating the feasibility of compensating for hysteresis and creep. The feedback signal to the PZT actuators is fed from differential capacitive sensors of the displacement of the microstage. Experimental results show that the sensitivity of the displacement sensor is approximately 0.53 V µm−1. A maximum resolution of 16 nm is achieved when hysteresis is compensated for, and the minimum detectable variation of capacitance ΔC is 1.25 × 10−3 pF. The hysteresis of the system varies with the proportional gain Kp, integral time constant Ti and reference input frequency. By using feedback control with a proportional and integration (PI) controller, the hysteresis decreases from 30% in open-loop operation to approximately 1% in closed-loop operation at a gain of 20, when the frequency of the sine reference input is 1 Hz and Ti is 20 ms. Efficient compensation of hysteresis is validated by the closed-loop control, especially when the frequency of the reference input is low. Elimination of creep/drift is also verified by the closed-loop control.

The Design and Analysis of a DLL-Based Frequency Synthesizer for UWB Application

A delay-locked loop (DLL)-based frequency synthesizer is designed for the ultrawideband (UWB) Mode-1 system. This frequency synthesizer with 528-MHz input reference frequency achieves less than 9.5-ns settling time by utilizing wide loop bandwidth and fast-settling architecture. Additionally, a discrete-time model of the DLL and an analytical model of phase noise of the delay line are proposed in this work. Experimental results show great consistency with predicted settling time and phase noise. The circuit has been fabricated in a 0.18-/spl mu/m CMOS technology and consumes only 54 mW from a 1.8-V supply. It exhibits a sideband magnitude of -35.4 dBc and -120-dBc/Hz phase noise at the frequency offset of 1 MHz.