Abstract
A high speed low power consumption positive edge triggered Delayed (D) flip-flop was designed for increasing the speed of counter in Phase locked loop, using 180 nm CMOS technology. The designed counter has been used in the divider chip of the phase locked loop. A divide counter is required in the feedback loop to increase the VCO frequency above the input reference frequency. The proposed circuit is faster than conventional circuit as it has fast reset operation. The circuit consumes less power as it prevents short circuit power consumption. The circuit operates at 1.8V power supply. This work has been used in the design. of 2.4 GHz CMOS PLL targeting OFDM application. The CMOS based fast D-ff circuit has designed and simulated by Virtuoso tool of CADENCE spectre
Highlights
D flip-flop is an important part of the modern digital circuits
Phase locked loops are built of a detector, charge pump, low pass filter, voltage-controlled oscillator (VCO) and frequency divider placed in a negative feedback closed-loop configuration
To form a phase-locked loop (PLL), the phase error output of Phase frequency detector (PFD) is fed to a charge pump and to loop filter which integrates the signal to get a sharper and smooth signal so that the disturbances at the input of VCO get minimized
Summary
D flip-flop is an important part of the modern digital circuits. Phase locked loop with an excellent performance is widely studied in recent years. Edge Triggered D flip flops are often implemented in integrated high speed operations using dynamic logic. This means that the digital output is stored on parasitic device capacitance while the device is not transitioning. The conventional D flip-flop which uses E-TSPC logic has higher operating frequencies but it features static power dissipation This causes small increase in power dissipation, since at the frequencies of interest dynamic power consumption is dominant. Phase locked loops are built of a detector, charge pump, low pass filter, voltage-controlled oscillator (VCO) and frequency divider placed in a negative feedback closed-loop configuration. The output is locked to the frequency at the other input
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