Input-queued Switches Research Articles

A logarithmic scheduling algorithm for high speed input-queued switches

Throughput of input queued switches using FIFOs is limited due to the Head of Line blocking (HoL) problem. Using VOQs at inputs and a proper scheduling algorithm, near 100% throughput can be achieved. Scaling in terms of number of ports and line rates is a crucial factor for switches deployed in very high speed networks. We propose a novel scheduler called DHL, Decomposed Hierarchical Logarithmic, which is faster than schedulers like iSLIP while performing better for bursty and IP traffics. DHL supports priority in a manner better than other input queue switches especially for bursty traffics. We also propose an optimal version of DHL which is fairer while having half of DHL’s area. By pipelining, it is also possible to increase its speed 2 times. DHL scales well in terms of performance, area, and delay. Its area scales linearly with the number of input ports and its delay grows logarithmically while its performance remains almost constant. Our scheduler can be implemented with a low complexity, while working with different service policies like Round Robin, RR, and Earliest Deadline First, EDF. We report our simulation results regarding the average delay, throughput, burst reduction, fairness and priority with respect to the switch sizes.

Captured-frame matching schemes for scalable input-queued packet switches

Single-stage input-queued (IQ) switches are attractive for implementation of high performance routers because they require no speedup in the used memory. It has been shown that IQ switches can provide 100% throughput under admissible traffic when using maximum-weight matching schemes or iterative maximal-weight matching schemes with a speedup of two or more. These different approaches require either high computation complexity or high memory costs that can make them infeasible. Therefore, there is a need for low-complexity and fast matching schemes that provide high throughput under several admissible traffic patterns, including those with nonuniform distributions, without recurring to speedup nor multiple iterations. In this paper, we introduce the concept of captured frame and apply it to matching schemes. As a result, we propose two weightless matching schemes, one based on round-robin selection, called uFORM, and the other based on random selection, called uFPIM. We analyze the throughput improvement achieved by uFPIM, and show that these matching schemes provide high throughput under a variety of admissible traffic patterns, including those with nonuniform distributions, when using a single iteration and no speedup. Furthermore, we study the scalability of the captured-frame concept in matching schemes for memory-space-memory multiple-stage Clos-network switches, and show the achieved high switching performance and low implementation complexity.

An efficient scheduling algorithm for input-queued switches

This letter presents an efficient scheduling algorithm DTRR (Dual-Threshold Round Robin) for input-queued switches. In DTRR, a new matched input and output by round robin in a cell time will be locked by two self-adaptive thresholds whenever the queue length or the wait-time of the head cell in the corresponding Virtual Output Queue (VOQ) exceeds the thresholds. The locked input and output will be matched directly in the succeeding cell time until they are unlocked. By employing queue length and wait-time thresholds which are updated every cell time simultaneously, DTRR achieves a good tradeoff between the performance and hardware complexity. Simulation results indicate that the delay performance of DTRR is competitive compared to other typical scheduling algorithms under various traffic patterns especially under diagonal traffic.

An Efficient Packet Scheduling Algorithm With Deadline Guarantees for Input-Queued Switches

Input-queued (IQ) switches overcome the scalability problem suffered by output-queued switches. In order to provide differential quality of services (QoS), we need to efficiently schedule a set of incoming packets so that every packet can be transferred to its destined output port before its deadline. If no such a schedule exists, we wish to find one that allows a maximum number of packets to meet their deadlines. Recently, this problem has been proved to be NP-complete if three or more distinct deadlines (classes) are present in the set. In this paper, we propose a novel algorithm named Flow-based Iterative Packet Scheduling (FIPS) for this scheduling problem. A key component in FIPS is a non-trivial algorithm that solves the problem for the case where two classes are present in the packet set. By repeatedly applying the algorithm for two classes, we solve the general case of an arbitrary number of classes more efficiently. Applying FIPS to a frame-based model effectively achieves differential QoS provision in IQ switches. Using simulations, we have compared FIPS performance with five well-known existing heuristic algorithms including Earliest-Deadline-First (EDF), Minimum-Laxity-First (MLF) and their variants. The simulation results demonstrate that our new algorithm solves the deadline guaranteed packet scheduling problem with a much higher success rate and a much lower packet drop ratio than all other algorithms.

Degree-sequenced matching algorithms for input-queued switches

This paper presents a class of algorithms for scheduling packets in input-queued switches. As opposed to previously known algorithms that focus only on achieving high throughput, these algorithms seek to achieve low average delay without compromising the throughput achieved. Packet scheduling in input-queued switches based on the virtual-output-queued architecture is a bipartite graph matching problem wherein ports are represented by vertices and the traffic flows by the edges. The set of matched edges determine the packets that are to be transferred from the input ports to the output ports. Current matching algorithms implicitly prioritize high-degree vertices, i.e., ports with a large number of flows, causing longer delays at ports with a smaller number of flows. Motivated by this observation, we present three matching algorithms based on explicitly prioritizing low-degree vertices and the edges through them. Using both real gateway traffic traces as well as synthetically generated traffic, we present simulation results showing that this class of algorithms achieves a low average delay as compared to other scheduling algorithms of equivalent complexity while still achieving similar throughput. We also show that these algorithms determine the maximum size matching in almost all cases.

Approximating Fluid Schedules in Crossbar Packet-Switches and Banyan Networks

We consider a problem motivated by the desire to provide flexible, rate-based, quality of service guarantees for packets sent over input queued switches and switch networks. Our focus is solving a type of online traffic scheduling problem, whose input at each time step is a set of desired traffic rates through the switch network. These traffic rates in general cannot be exactly achieved since they assume arbitrarily small fractions of packets can be transmitted at each time step. The goal of the traffic scheduling problem is to closely approximate the given sequence of traffic rates by a sequence of transmissions in which only whole packets are sent. We prove worst-case bounds on the additional buffer use, which we call backlog, that results from using such an approximation. We first consider the NtimesN, input queued, crossbar switch. Our main result is an online packet-scheduling algorithm using no speedup that guarantees backlog at most (N+1) <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2 </sup> /4 packets at each input port and each output port. Upper bounds on worst-case backlog have been proved for the case of constant fluid schedules, such as the N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> -2N+2 bound of Chang, Chen, and Huang (INFOCOM, 2000). Our main result for the crossbar switch is the first, to our knowledge, to bound backlog in terms of switch size N for arbitrary, time-varying fluid schedules, without using speedup. Our main result for Banyan networks is an exact characterization of the speedup required to maintain bounded backlog, in terms of polytopes derived from the network topology

Quality of service provision in combined input and crosspoint queued switches without output queueing match

Packet switches play one of the most critical roles in supporting quality of service (QoS) in computer communication networks. Although the output queued (OQ) switch architecture can achieve optimal QoS performance, it is not a practical architecture for high-speed switching due to the switching fabric speedup, which requires complex implementation. Combined input and crosspoint queued (CICQ) switches employ the crossbar-based switching fabric structure and apply buffers at both ingress port modules and crosspoints inside the switching fabric. This switch architecture is promising to achieve high performance without complex implementation. Current available approaches for QoS provision in CICQ switches are based on the output queueing match technique. Although such approaches can provide bandwidth and delay guarantees, they still require switching fabric speedup, which may significantly increase the implementation complexity of high-speed CICQ switches. In this paper, we compare the QoS performance that can be achieved in CICQ switches with the QoS performance guaranteed by OQ switches. Based on this comparison, we investigate the possibility of achieving equivalent QoS guarantees in a CICQ switch as in an OQ switch without output queueing match, thus with no switching fabric speedup. Our analysis shows that if sufficient crosspoint buffer space is allocated, a CICQ switch employing a typical scheduling algorithm, such as weighted fairing queueing (WFQ), can provide an identical bandwidth guarantee as the OQ switches without any switching fabric speedup, and can achieve equivalent delay performance as the OQ switch by slightly increasing bandwidth allocation.

Low complexity, stable scheduling algorithms for networks of input queued switches with no or very low speed-up

The delay and throughput characteristics of a packet switch depend mainly on the queueing scheme and the scheduling algorithm deployed at the switch. Early research on scheduling algorithms has mainly focused on maximum weight matching scheduling algorithms. It is known that maximum weight matching algorithms guarantee the stability of input-queued switches, but are impractical due to their high computational complexity. Later research showed that the less complex maximal matching algorithms can stabilize input-queued switches when they are deployed with a speed-up of two. For practical purposes, neither a high computational complexity nor a speed-up of two is desirable.In this paper, we investigate the application of matching algorithms that approximate maximum weight matching algorithms to scheduling problems. We show that while having a low computational complexity, they guarantee the stability of input queued switches when they are deployed with a moderate speed-up.In particular, we show that the improve_matching algorithm stabilizes input-queued switches when it is deployed with a speed-up of 3&lt;over&gt;2+ε.In a second step, we further improve on these results by proposing a class of maximal weight matching algorithms that stabilize an input-queued switch without any speed-up.Whereas initial research has only focused on scheduling algorithms that guarantee the stability of a single switch, recent work has shown how scheduling algorithms for single switches can be modified in order to design distributed scheduling algorithms that stabilize networks of input-queued switches. Using those results, we show that the switching algorithms proposed in this paper do not only stabilize a single switch, but also networks of input-queued switches.

Modeling of the priority scheduling input—line group output with multi-channel in ATM exchange system

In this paper, an extended Kendall model for the priority scheduling input—line group output with multi-channel in Asynchronous Transfer Mode (ATM) exchange system is proposed and then the mean method is used to model mathematically the non-typical non-anticipative PRiority service (PR) model. Compared with the typical and non-anticipative PR model, it expresses the characteristics of the priority scheduling input—line group output with multi-channel in ATM exchange system. The simulation experiment shows that this model can improve the HOL block and the performance of input-queued ATM switch network dramatically. This model has a better developing prospect in ATM exchange system.

A Simulation-Based Comparison of Multimedia Traffic Prioritization Schemes for High-Performance Input-Queued Packet Switches

This study investigates the problem of enabling Quality of Service (QoS) of multimedia traffic at the input port of high-performance input-queued packet switches using a simulation-based evaluation. We focus on the possibility of assuring QoS of multimedia traffic in such switches by implementing traffic prioritization at the input port where each input-queue has been modified to provide a separate buffer for each of the service classes. The multimedia traffic can be categorized into three classes based on its real-time properties and loss tolerance and assigned a separate queue for each class. We select appropriate models for each of three types of traffic: video, voice and data. Then, we propose an efficient dynamic scheduling strategy by implementing multimedia traffic prioritization at the input port of input-queued packet switches. Simulation-based comparisons show that while the static priority scheme is beneficial for highest priority class at the expense of the others, the dynamic prioritization serves fairly well all the classes in terms of delay and loss requirements.

On guaranteed smooth scheduling for input-queued switches

Input-queued switches are used extensively in the design of high-speed routers. As switch speeds and sizes increase, the design of the switch scheduler becomes a primary challenge, because the time interval for the matching computations needed for determining switch configurations becomes very small. Possible alternatives in scheduler design include increasing the scheduling interval by using envelopes , and using a frame-based scheduler that guarantees fixed rates between input-output pairs. However, both these alternatives have significant jitter drawbacks: the jitter increases with the envelope size in the first alternative, and previously-known methods do not guarantee tight jitter bounds in the second. In this paper, we propose a hybrid approach to switch scheduling. Traffic with tight jitter constraints is first scheduled using a frame-based scheduler that achieves low jitter bounds. Jitter-insensitive traffic is later scheduled using an envelope-based scheduler. The main contribution of this paper is a scheduler design for generating low-jitter schedules. The scheduler uses a rate matrix decomposition designed for low jitter and different from the minimum-bandwidth Birkhoff-Von Neumann (BV) decomposition. In addition to generating low-jitter schedules, this decomposition in the worst case yields fewer switch configuration matrices (O(n)) than the BV decomposition (O(n/sup 2/)), and so requires far less high-speed switch memory. We develop an efficient algorithm for decomposing the rate matrix and for scheduling the permutation matrices. We prove that our low-jitter algorithm has an O(logn) factor bound on its bandwidth consumption in comparison to the minimum-bandwidth BV decomposition. Experimentally, we find that the bandwidth increase in practice is much lower than the theoretical bound. We also prove several related performance bounds for our scheduler. Finally, we propose a practical algorithm for bandwidth-guaranteed algorithm, and show how our findings could even be extended to systems with large tuning time.

Packet-Mode Scheduling with Proportional Fairness for Input-Queued Switches

Proportional fair bandwidth allocation in packet switches is a fundamental issue to provide quality of service (QoS) support in IP networks. In input-queued switches, packet-mode scheduling delivers all the segments of a packet contiguously from the input port to the output port, thus greatly simplifying the design of packet reassembly modules and yielding performance advantage over cell-mode scheduling under certain conditions [1]. One of the important issues of packet-mode scheduling is how to achieve fair bandwidth allocation among flows with different packet sizes. This paper presents an algorithm called packet-mode fair scheduling (pFS) that guarantees each flow a bandwidth proportional to its reservation regardless of the packet size distribution and the system load. Simulations show that our approach achieves good fairness as well as high throughput and low packet delay. Compared to algorithms without fairness mechanism, pFS yields significant performance improvement in terms of average packet delay when the traffic is heterogeneous. A hardware implementation is presented to show that the proposed algorithm has low complexity and the computation can be completed in a single clock cycle, which makes pFS applicable to high-speed switches.

Stability of a frame-based maximal weight matching algorithm with transfer speedup

It has been shown that maximal size matching algorithms for input-queued switches are stable under any admissible traffic conditions with a scheduling speedup of 2. However, as link speeds increase, the computational complexity of these algorithms limits their applicability in high port-density switches and routers. In this letter we describe a Frame-Based Maximal Weight Matching (FMWM) algorithm in which a new scheduling decision is issued once every several cell times. Between scheduling decisions, the configuration of the crossbar switch remains unchanged. We prove that the FMWM algorithm is stable with an internal buffer transfer speedup of 2, thereby significantly relaxing the timing constraints on the scheduling process. Simulation results illustrate the impact of the algorithm on the average cell delay for different traffic scenarios.

Cell switching versus packet switching in input-queued switches

Input Queued (IQ) switches have been well studied in the past two decades by researchers. The main problem concerning IQ switches is scheduling the switching fabric in order to transfer packets from input ports to output ports. Scheduling is relatively easier when all packets are of the same size. However, in practice, packets are of variable length. In the current implementation of switches, variable length packets are segmented into fixed length packets-also knowns as cells-for the purpose of scheduling. However, such cell-based switching comes with some significant disadvantages: (a) loss of bandwidth due to the existence of incomplete cells; and (b) additional overhead of segmentation of packets and re-assembly of cells. This is a strong motivation to study packet-based scheduling, i.e., scheduling the transfer of packets without segmenting them. The problem of packet scheduling was first considered by Marsan et al. They showed that under any admissible Bernoulli IID (independent and identically distributed) arrival traffic, a simple modification of the Maximum Weight Matching (MWM) algorithm achieves 100% throughput. In this paper, we first show that no work-conserving (i.e., maximal) packet-based algorithm is stable for arbitrary admissible arrival processes. Thus, the results of Marsan et al. are strongly dependent on the arrival distribution. Next, we propose a new class of waiting algorithms. We show that the waiting-MWM algorithm is stable for any admissible traffic using the fluid limit technique. We would like to note that the algorithms presented in this paper are distribution independent or universal. The algorithms and proof methods of this paper may be useful in the context of other scheduling problems.

An integrated scheduling and buffer management scheme for input queued switches with finite buffer space

This paper addresses scheduling and memory management in input queued switches having finite buffer with the objective of improving the performance in terms of throughput and average delay. Most of the prior works on scheduling related to input queued switches assume infinite buffer space. In practice, buffer space being a finite resource, special memory management scheme becomes essential. Maximum weighted matching (MWM) algorithm, which is known to be the optimal in terms of throughput for infinite buffer case turns out to be sub optimal in the presence of memory limitations. We introduce a buffer management scheme called iSMM (Integrated Scheduling and Memory Management) that can be employed jointly with any deterministic iterative scheduling algorithm. We applied iSMM over iSLIP, a popular scheduling algorithm, and study its effect under various input traffic conditions. Simulation results indicate iSMM to perform better than iSLIP and MWM both in terms of throughput and delay especially under non-uniform traffic.

On the Stability of Isolated and Interconnected Input-Queueing Switches Under Multiclass Traffic

In this correspondence, we discuss the stability of scheduling algorithms for input-queueing (IQ) and combined input/output queueing (CIOQ) packet switches. First, we show that a wide class of IQ schedulers operating on multiple traffic classes can achieve 100% throughput. Then, we address the problem of the maximum throughput achievable in a network of interconnected IQ switches and CIOQ switches loaded by multiclass traffic, and we devise some simple scheduling policies that guarantee 100% throughput. Both the Lyapunov function methodology and the fluid modeling approach are used to obtain our results.

Packet scheduling in input-queued switches with a speedup of less than two and scheduling algorithms for switches with a configuration overhead

Input-queued switches and the solution of input/output contention by scheduling algorithms have been widely investigated. Most research has focused on switches for fixed-size packets. This contrasts with the variable size packets of IP networks. Previous research on fixed packet length has only focused on maximum weight matching algorithms. As maximum weight matching algorithms are computationally very complex, it is of interest to investigate less complex, but stable algorithms that take into account the variable packet size of data packets. In this paper, we investigate how the class of maximal matching algorithms deployed in switches with a speedup of less than two can be modified to take into account the varying packet sizes. Using a novel model for the dynamics of maximal matching algorithms, we show that modified maximal matching algorithms guarantee stability of the switch and establish bounds on the average delay experienced by a packet. In the second part of the paper, we apply the techniques developed for networks with variable packet size to the design of a scheduling algorithm for switches with large configuration overhead. We design a maximal weight matching algorithm for a switch with configuration overhead and determine the minimum speedup required to guarantee the stability of the switch.

A multiple input-queued ATM switching fabric based on hopfield neural network cell scheduling

A multiple input-queued ATM switching fabrics (ASF) for scheduling cell based on Hopfield neural network (HNN) is proposed. This scheme eliminates degeneration of performance due to head-of-line (HOL) blocking. Simulation results show that, compared with the single first in_first out and window input-queued ASF, the pr oposed approach can greatly improve the throughput and reduce the cell delay.

Mathematical analysis of the input-queued packet switch under multicast traffic

This paper deals with input-queued packet switches loaded with multicast traffic. An (N×N) packet switch is considered, operating in a synchronous slotted fashion, on fixed-size data units (called interchangeably as cells or fixed-length packets). A switch scheduler identifies a set of non-conflicting inputs during each time slot. Since service of multiple cells from the same input requires internal speed-up or switch fabric expansion, it is assumed that the switch follows the restricted rule i.e., only one cell can be switched from one input port and only one cell can be switched to one output port during one time slot. The performance of such a switch is analysed and the equations for the performance metrics such as saturation throughput, mean cell delay and average queue length are derived. It is assumed that there are 2N−1 queues at each input port to achieve optimal switch performance. While this may not be possible for large switch sizes, it is believed that it is necessary to use switches of smaller sizes with 2N−1 queues at each input, to completely eliminate head-of-line blocking and achieve optimal performance.

A Round-Robin Scheduling Algorithm by Iterating Between Slots for Input-Queued Switches

Input-Queueing is becoming increasingly used for high-bandwidth switches and routers for its scalability, but it needs an elaborate scheduling algorithm to achieve good performance. Round-Robin algorithms have been extensively investigated due to its simplicity and parallelism. However, the present Round-Robin algorithms suffer from poor performance under nonuniform and burst traffic. This paper proposes a Round-Robin algorithm named iSLOT, which can approximate the maximum matching algorithms by iterating the scheduling decision between slots and using the randomness of the queue length. Simulation results show that iSLOT not only is stable under uniform i.i.d traffics, but also outperforms the existing round-robin algorithms under burst and nonuniform traffics in throughput and delay performance.