Input Circuit Research Articles

Coin-Based Mobile Phone Charger with High Security

Mobile phones are phenomenal in recent years for communication as well as in day-to-day life. Hence, charging the mobile phones has become the greater task. In this project; we are trying to design a mobile battery charger on coin insertion. As uses of mobile phones are increasing day by day it need battery life all the time, so in order to use them public charging is needed which would be useful for mobile users. This system will charge the mobile phone for a particular time-period. When the valid coin is recognized, it will start giving power supply to the cell phone through one of the adapters. We will be using a global charging adapter that would be suitable for all mobile phones. The mentioned system can be implemented in public places like railway stations, bus stops, hospitals, malls, etc. to avail the services. The objective of this project is inserting the coin using charge for your mobile phone in public places. This project is very useful to people who are all using mobile phone without charging condition in public places. In this project, who are all using mobile phones in outside of home are office without charging condition. The coin-based mobile phone charger is very useful to that person for using coin to charge for that mobile. The IR (infrared) transmitter is used to transmit IR signal in the transmitter side. The IR receiver is used to receive the IR signal in the receiver side. Between the IR transmitter and receiver, insert a coin to change the polarity of pulse in SCU input. The SCU is used to converting low pulse to high pulse and that pulse is inverted in inverter. The 555 IC is act as a timer to produces high pulse for particular time period. Again the SCU is used to converting low pulse to high pulse and this output is give to input of driver circuit. Driver circuit is used for provide the sufficient input voltage of relay. The relay will on to activate the 230v charger, we will use charger to charge for our mobile phone. Key Word: Mobile Phone, Atmega Microcontroller, Coin acceptor, LCD display, SMPS, Relay

A Dual-Polarized Aperture-Sharing Phased-Array Antenna for 5G (3.5, 26) GHz Communication

Integrating the sub-6 GHz antenna and the millimeter-wave (mm-wave) antenna in one radiating aperture is a promising approach to support different frequency bands for the incoming communication system. In this paper, an mm-wave dual-polarized 64-element phased-array antenna is integrated into the partially reflective surface (PRS) of a sub-6 GHz resonant cavity antenna (RCA). The PRS consists of two multi-layer printed circuit boards (PCBs), which are stacked together and connected by solder joints. The thick PRS unit cell is designed with a miniaturized footprint at 3.5 GHz and can also contain a 2 × 2 mm-wave active subarray, including four stacked-patch antennas, a beamformer IC (BFIC), and some other input circuits. A copper plate is also inserted in the PRS for thermal control. A prototype antenna is fabricated and measured. Measurement results agree well with the simulation. In the sub-6 GHz band, the proposed antenna demonstrates dual-polarized radiation over the frequency band from 3.45 GHz to 3.58 GHz. In the high-frequency band, the dual-polarized mm-wave array driven by the built-in active beamforming network is capable of scanning ± 45° both in azimuth and elevation over the frequency band from 24.5 GHz to 27 GHz.

A Low-Cost Burn-In Tester Architecture to Supply Effective Electrical Stress

Burn-In test equipment usually owns extensive memory capabilities to store pre-computed patterns to be applied to the circuit inputs as well as ad-hoc circuitries to drive and read the DUT pins during the BI phase. The solution proposed in this paper dramatically reduces the memory size requirement and just demands a generic microcontroller unit (MCU) equipped with a couple of embedded processors, some standard common peripheral units, and a few KB memories. Moreover, the proposed Burn-In tester could be integrated into a System Level Test equipment which is typically based on MCUs to communicate functionally with the DUT. This paper provides full details about the architecture of such a low-cost innovative tester, which can supply the DUT with unlimited pseudo-random patterns created autonomously by the MCU firmware from any selected seed. The tester prototype developed to collect experimental results includes a low-cost System-on-Chip based on a multi-core MCU and a set of peripheral cores, encompassing timers and Direct Memory Access modules. The tester prototype is used to stress an automotive chip accounting for about 20 million gates, 700 thousand scan flip-flops, and several scan modes. The combination of pseudo-random pattern generation with the ability to control different scan and Design for Testability (DfT) modes, including LBIST, permits to reach a higher coverage of stress metrics than by the application of a limited set of pre-computed ATPG patterns. The toggle coverage level reached is up to 95.89%. The application speed achieved by the tester with non-optimized connections is up to about 10MHz.

Программно-аппаратное обеспечение исследования электромагнитных излучений, создаваемых вычислительной техникой, в бытовой электрической сети

Solution of the urgent scientific and technical problem in the field of information security – the problem of detecting electromagnetic radiation generated by computing aids – has been considered as part of studying radiation in the household electrical network. Developing an interface for coordination of a program-defined radio system with a household electrical network has been shown and a methodology for estimating the volume of the studied radiation in it has been proposed. Two matching units have been made: the first unit allocates a differential variable of the high-frequency component. The second unit distributes a cophased variable. To separate a low-frequency component and cut off the high low-frequency voltage, high-voltage ceramic capacitors were used. To protect the input from possible high-voltage pulses and noises, as well as half of the mains voltage, matching transformers on high-frequency ferrite were used. The components of the matching units are located inside the network plugs, and the SMA output slots are used to connect the receiver. A bandpass filter with a bandwidth of 50–500 MHz was developed as an additional mechanism for protecting the input circuits of the receiver. This range overlapped the necessary frequency range with a margin. Using the filter made it possible to additionally protect the SDR input of the receiver from high-voltage and broadband network interference, as well as to reduce the influence of the unwanted radiation on the receiver's ADC. The algorithm and methodology of registration, measurement and comparison of some quantitative parameters of electromagnetic radiation generated by computer technology are proposed. The revealed regularities indicate that weak signals of the studied radiation broadcast into the air are a potentially less energy-armed threat to the information security than electromagnetic emissions entering the electrical networks.

A non-pipelined ADC with a GM-R amplifier

A GM-R amplifier is proposed as a residual amplifier to implement a 16-bit two-stage non-pipelined ADC in intermittent signal acquisition applications. Unlike common capacitive feedback amplifiers, residual amplifiers utilize resistor ratios to generate constant gain for small input amplitude ranges and wide temperature ranges. The input circuit of the proposed amplifier consists of two source followers and a bridge resistor, thus converting residual voltages to currents, and the transconductance is the reciprocal of the bridge resistor. The amplifier offset voltage is corrected by a one-time foreground offset calibration, and the gain error is calibrated with the capacitor weights in the first stage. Redundancy is adopted between the two stages to accommodate the residual offset voltage after calibrating the offset voltage of a comparator and the gain variation. A design prototype is implemented in 180 nm CMOS technology, occupies a 0.69 mm2 footprint, and consumes 3.0 mW from 1.8/5 V power supplies. After calibration, it achieves the SNR of 88.2 dB, SNDR of 87.6 dB, and THD of −95.6 dB at 200 kHz sampling rate. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.62/+0.74 LSB and −1.39/+1.50 LSB, respectively.

On the Evolutionary Synthesis of Fault-Resilient Digital Circuits

In the event of an upset, fault-resilient circuits maintain correct functionality allowing the system to remain fully operational or at least operate with a graceful degradation. Every circuit has a certain level of inherent resilience to faults. Often times, this inherent resilience to faults is insufficient for the given application. This is because conventional synthesis tools generally only focus on optimizing a circuit with respect to area, power, or timing budgets. There is a wide range of applications where faulty circuit behavior can lead to fatal results. Fault injection analyses are reported and show that even a single fault can be critical to the desired circuit operation. To which end, this article presents synthesis of fault-resilient (SYFR) circuits, an evolutionary method for automated synthesis of increased fault-resilience digital circuits suitable for fine-grained use. Test results for synthesis of up to 60 input circuits with SYFR are reported. SYFR can be repeatedly applied to a circuit to obtain various design tradeoffs between fault resilience and implementation costs. SYFR can also be flexibly applied to build circuits, which are selectively fault resilient, i.e., their tolerance to faults is workload aware. In addition, a novel population seeding mechanism to reduce the design space is introduced and experimentally validated. In summary, this article demonstrates that SYFR can be considered a competitive synthesis methodology for constructing fault-resilient circuits.

Suppressing Quantum Circuit Errors Due to System Variability

We present a quantum circuit optimization technique that takes into account the variability in error rates that is inherent across present day noisy quantum computing platforms. This method can be run post qubit routing or post-compilation, and consists of computing isomorphic subgraphs to input circuits and scoring each using heuristic cost functions derived from system calibration data. Using an independent standard algorithmic test suite we show that it is possible to recover on average nearly 40% of missing fidelity using better qubit selection via efficient to compute cost functions. We demonstrate additional performance gains by considering qubit placement over multiple quantum processors. The overhead from these tools is minimal with respect to other compilation steps, such as qubit routing, as the number of qubits increases. As such, our method can be used to find qubit mappings for problems at the scale of quantum advantage and beyond.

Analysis of ionic equilibria by water treatment stage and calculation of monitored parameters

The mathematical model of the unit of the water treatment scheme is based on the mathematical model of improvements in the consistency metrics by step of treatment and is the basis for the technical measurement of this element. The suggested step-by-stage estimation of the water quality indicators for the assembled water treatment unit system helps the final quality of the treated water to be calculated and the mathematical model of the quality indicators adjustment by treatment phase was developed in relation to the water used in the TPP water treatment. For circuit elements, the change in the input and output quality indicators occurs depending on the type of processing, which is conveniently represented by equivalent circuits. For circuit elements, input and output quality variation occurs depending on the type of processing, which is conveniently represented by equivalent circuits. Thus, an equivalent scheme for the change in quality indicators by treatment stage can be represented by the example of a one-stage chemical desalination scheme for natural water. It should be noted that the calculated concentration fractions of carbon dioxide dissociation forms and known carbonate hardness, for example, can be used to determine the concentrations themselves.

A New Tapped Inductor Buck Converter with Large Step-Down Voltage Conversion

This paper presents a new DC(DC converter with large step-down voltage conversion. The proposed converter is obtained by cascading an input circuit of a Quadratic Buck Converter (QBC) to a Tapped Inductor Buck Converter (TIBC). It uses only one active switch and provides a wider voltage conversion range than other well-known step-down converters. In the paper, the operation of the proposed converter is described. Circuit analysis is performed to derive the voltage gain and key current and voltage equations. The prototype circuit operating with the input voltage of 150 V, the output voltage of 5 V, the load current of 10 A and the switching frequency of 100 kHz is implemented. Experimental results show that the prototype converter exhibits good output voltage regulation and achieves the 30-to-1 voltage step-down operation with a maximum efficiency of 82%. In addition, measurement results confirm that the converter operation is consistent with the theoretical analysis.

Whole-brain input mapping of the lateral versus medial anterodorsal bed nucleus of the stria terminalis in the mouse

The anterior portion of the bed nucleus of the stria terminalis (BNST) modulates fear and stress responses. The anterodorsal BNST (adBNST) can be anatomically subdivided further into the lateral and medial divisions. Although output projections of BNST subregions have been studied, the local and global input connections to these subregions remain poorly understood. To further understand BNST-centered circuit operations, we have applied new viral-genetic tracing and functional circuit mapping to determine detailed synaptic circuit inputs to lateral and medial subregions of adBNST in the mouse. Monosynaptic canine adenovirus type 2 (CAV2) and rabies virus-based retrograde tracers were injected in the adBNST subregions. The amygdalar complex, hypothalamus and hippocampal formation account for the majority of overall inputs to adBNST. However, lateral versus medial adBNST subregions have distinct patterns of long-range cortical and limbic brain inputs. The lateral adBNST has more input connections from prefrontal (prelimbic, infralimbic, cingulate) and insular cortices, anterior thalamus and ectorhinal/perirhinal cortices. In contrast, the medial adBNST received biased inputs from the medial amygdala, lateral septum, hypothalamus nuclei and ventral subiculum. We confirmed long-range functional inputs from the amydalohippocampal area and basolateral amygdala to the adBNST using ChR2-assisted circuit mapping. Selected novel BNST inputs are also validated with the AAV axonal tracing data from the Allen Institute Mouse Brain Connectivity Atlas. Together, these results provide a comprehensive map of the differential afferent inputs to lateral and medial adBNST subregions, and offer new insight into the functional operations of BNST circuitry for stress and anxiety-related behaviors.

Quantum error mitigation by Pauli check sandwiching

We describe and analyze an error mitigation technique that uses multiple pairs of parity checks to detect the presence of errors. Each pair of checks uses one ancilla qubit to detect a component of the error operator and represents one layer of the technique. We build on the results on extended flag gadgets and put it on a firm theoretical foundation. We prove that this technique can recover the noiseless state under the assumption of noise not affecting the checks. The method does not incur any encoding overhead and instead chooses the checks based on the input circuit. We provide an algorithm for obtaining such checks for an arbitrary target circuit. Since the method applies to any circuit and input state, it can be easily combined with other error mitigation techniques. We evaluate the performance of the proposed methods using extensive numerical simulations on 1850 random input circuits composed of Clifford gates and non-Clifford single-qubit rotations, a class of circuits encompassing most commonly considered variational algorithm circuits. We observe average improvements in fidelity of 34 percentage points with six layers of checks.

Three-dimensional mapping in multi-samples with large-scale imaging and multiplexed post staining

Dissection of the anatomical information at the single-cell level is crucial for understanding the organization rule and pathological mechanism of biological tissues. Mapping the whole organ in numerous groups with multiple conditions brings the challenges in imaging and analysis. Here, we describe an approach, named array fluorescent micro-optical sectioning tomography (array-fMOST), to identify the three-dimensional information at single-cell resolution from multi-samples. The pipeline contains array embedding, large-scale imaging, post-imaging staining and data analysis, which could image over 24 mouse brains simultaneously and collect the slices for further analysis. With transgenic mice, we acquired the distribution information of neuropeptide somatostatin neurons during natural aging and compared the changes in the microenvironments by multi-component labeling of serial sections with precise co-registration of serial datasets quantitatively. With viral labeling, we also analyzed the input circuits of the medial prefrontal cortex in the whole brain of Alzheimer’s disease and autism model mice. This pipeline is highly scalable to be applied to anatomical alterations screening and identification. It provides new opportunities for combining multi-sample whole-organ imaging and molecular phenotypes identification analysis together. Such integrated high-dimensional information acquisition method may accelerate our understanding of pathogenesis and progression of disease in situ at multiple levels.

On Test Sets Concerning Local Stuck-at Faults of Fixed Multiplicity at the Inputs of Circuits

On Test Sets Concerning Local Stuck-at Faults of Fixed Multiplicity at the Inputs of Circuits

A NOVEL AGING MONITORING CIRCUIT

Year by year there are numerous new requirements set to the lifetime and reliability of integrated circuits (IC), particularly in medical spheres and automotive applications. Consistent with technology downscaling the device reliability issues are increasing, but the quality requirements become stronger. Nowadays the aging phenomenon is one of the critical issues in systems with longer lifetime. Therefore, the monitoring of aging and its consequence compensation have become one of the key parts for today’s ICs. A novel aging monitoring circuit is proposed in this paper. This new monitoring circuit monitors the aging degradation during lifetime of the IC and generates a binary co¬d¬e. This code is applied to the inputs of compensation circuits, which compensates the degrad¬ati¬on in the critical blocks throughout their lifetime. Monitoring circuit is realized with a 14 nm technology node and simulations proved the results’ validity.

Variational Quantum Process Tomography of Non-Unitaries.

Quantum process tomography is a fundamental and critical benchmarking and certification tool that is capable of fully characterizing an unknown quantum process. Standard quantum process tomography suffers from an exponentially scaling number of measurements and complicated data post-processing due to the curse of dimensionality. On the other hand, non-unitary operators are more realistic cases. In this work, we put forward a variational quantum process tomography method based on the supervised quantum machine learning framework. It approximates the unknown non-unitary quantum process utilizing a relatively shallow depth parametric quantum circuit and fewer input states. Numerically, we verified our method by reconstructing the non-unitary quantum mappings up to eight qubits in two cases: the weighted sum of the randomly generated quantum circuits and the imaginary time evolution of the Heisenberg XXZ spin chain Hamiltonian. Results show that those quantum processes could be reconstructed with high fidelities (>99%) and shallow depth parametric quantum circuits (d≤8), while the number of input states required is at least two orders of magnitude less than the demands of the standard quantum process tomography. Our work shows the potential of the variational quantum process tomography method in characterizing non-unitary operators.

Математическое моделирование трансформаторного устройства с короткозамкнутой обмоткой для преобразования однофазного тока в шестифазное напряжение

Представлена математическая модель трансформаторного устройства с короткозамкнутой обмоткой (ТУ с КО), осуществляющее преобразование однофазного входного тока в шестифазное напряжение, которое может быть использовано в релейной защите электрических сетей. На основе математической модели ТУ с КО получена система дифференциальных уравнений в пространстве состояний, необходимых для моделирования и анализа различных установившихся и переходных режимов работы электрических сетей. Использованы подходы теории пространства состояний для получения системы дифференциальных уравнений применительно к структуре ТУ с КО. Получена математическая модель ТУ с КО в форме уравнений в пространстве состояний, позволяющая из однофазного входного тока сформировать систему шестифазных выходных напряжений. На основе предлагаемой модели ТУ с КО создана возможность его применения во входных цепях измерительных органов релейной защиты электрических сетей и проведения исследований.

Hybrid Energy Management System Consisting of Battery and Supercapacitor for Electric Vehicle

This paper is mainly focused on Hybrid Energy Management System (HEMS) consisting ofBattery (BT) and Super capacitor (SC). Two energy sources connected in with same DC link in parallel manner with the help of Bidirectional DC-DC converter, which is used to separate control of power flow of each source. Here Permanent magnet dc motor (PMDC) motor used as a load and speed control of PMDC motor can be done by PWM method for this purpose chopper circuit is used. Input of chopper circuit is DC link and output of the chopper is given to PMDC motor. This method of energy management gives power splitting between two sources based on State of Charge (SOC) of each individual source during different state of vehicle such as acceleration, constant running and deceleration. Improved filter-based power splitting techniques is implemented. Three acceleration reference points were taken for power splinting at different SOC levels of both energy sources. Objective of this proposed method is best use of both the sources i.e. battery and supercapacitor and maximum use of supercapacitor energy at the time of transient conditions. Battery supply energy during normal running condition or very less load condition. Hence during transient condition SC directly react with system and gives peak power requirement, so stress on battery is reduces hence lifetime of battery is increase, also power available during braking is store in SC and battery, so independence of Electric Vehicle (EV) is increases. Because of less peak power requirement, batteries with less peak output power is used so it is reduced size and cost of batteries. Matlab-Simulink software is used for simulation and also small scale hardware is also implemented of proposed method.

Introduction of an additional source of harmonic signal into the circuit of the electric power resonant amplifier

Problem. The problems of the electric power industry, caused by the depletion of the natural resources of the planet and the need to replace them, initiate the development of new physical and technical solutions with the practical use of the known natural phenomena. Goal. The purpose of this work is to propose to introduce an additional source of a harmonic signal (voltage or current) into the circuit of a resonant amplifier of electric power, to obtain calculated analytical dependencies for numerical estimates of the characteristics of ongoing electromagnetic processes, which make it possible to give a fundamental justification for the real performance of the proposed circuit as a whole, taking into account the interaction of all its functional components. Methodology. This work, ultimately, involves the use of resonant phenomena in circuits with active-reactive elements and their theoretical analysis using the mathematical apparatus of the theory of electrical circuits. Results. It is proposed to implement the resonant amplifier circuit in the form of four active-reactive closed circuits inductively coupled to each other. Moreover, in a practical embodiment, inductive couplings can be carried out using HF ferrites. The first circuit is the input circuit with the harmonic power source to be amplified. The second circuit generates amplified reactive power in the "voltage resonance" mode. The third circuit with an additional harmonic voltage source outputs reactive power from the second circuit in the "current resonance" mode. The fourth circuit, inductively coupled to the third circuit, contains the output load of the entire resonant amplifier. This is a resistor that simulates the release of active power. Originality. Physically, the introduction of an additional source in the third circuit is equivalent to the creation of a "negative active resistance", which makes it possible to create conditions for excitation of current resonance with the minimum possible distortion and, ultimately, to reduce the reverse effect on the amplifying processes in the second circuit (reactive power amplifier). The analysis and numerical evaluation of the characteristics of the proposed scheme of the active electric power resonant amplifier showed its fundamental viability. Practical value. As an example, calculations of currents and voltages in the circuit of an experimental model were made, which enabled to formulate recommendations for the selection of elements of a real active electric power amplifier with high efficiency for low-resistance output loads.

PARAMETRIC CONTROL SYSTEM OF A THREE-PHASE ACTIVE RECTIFIER WITH A FIXED MODULATION FREQUENCY

The study of the characteristics of active controlled rectifiers – voltage sources (ARVS) is inextricably connected with the issue of using one or another key management algorithm in them. It is known that they are divided into two main groups: algorithms with a variable and with a fixed modulation frequency. Each of them has its advantages and disadvantages, bringing features both to the calculation of the parameters of the power circuit of the converter, and to the choice of the structure of the control system and autoregulation. Control algorithms with a fixed modulation frequency have tangible advantages that simplify the thermal calculation of circuit elements and input filters of the converter. In practice, most often, it is necessary to maintain the offset angle between the current and the voltage of the power network equal to 0, or, in the energy recovery mode – 180 electrical degrees. Parametric control systems cope well with this task. Therefore, is was shown creation and modeling the structure of the parametric control system of the ARVS with a fixed modulation frequency, which allows to form a power network current close to a sinusoid with a zero phase shift with respect to the network voltage in a wide range of changes in the parameters of the circuit and the power consumed by it. The paper examines: the physical prerequisites for the operation of the control system algorithm proposed by the authors, which is built on the principle of generating a PWM generator control signal from the component voltages of the input circuit of the circuit with phase correction of the shift angle of the first harmonic of the network current relative to the supply voltage; principles of formation of signals operating within it; the dependencies justifying the need to apply the technical solutions proposed in the article are built. The simulation results showed that the ARVS, which works with the proposed control system, allows maintaining the specified value of the output voltage and the current close to the sinusoid of the power network with zero phase shift relative to the power supply voltage in a wide range of changes in the parameters of the circuit and the power consumed by it.

Identifying Reliability-Critical Primary Inputs of Combinational Circuits Based on the Model of Gate-Sensitive Attributes

The identification of reliability-critical primary input leads (RCPIs) plays an important role in the testing and prediction of reliability boundaries of logic circuits. This article presents a gate-sensitive-attributes-based approach to estimate the criticality of the primary input leads in combinational circuits to their reliability. Oriented to the input vector, a subcircuit-based traversal method marks the critical input leads of each gate in a circuit. Gate-sensitive attributes and a reverse recursive algorithm quantify the effect of each RCPI on circuit reliability under the input vector. A parallel calculation method based on subcircuits with only one primary output reduces the computational complexity to accelerate the calculation process. Similarity-based clustering avoids unnecessary calculations, and a self-adaptive strategy is used to check convergence. Experimental results on benchmark circuits show that the average accuracy of this approach is 0.9634 with Monte Carlo (MC) as the reference and it is 3445 times faster than the MC on average while its average memory cost is 1.67 greater than the MC model. Although the fitness of the worst input vector obtained by other reference methods is 1.09 times better than that of this approach on average, this approach is approximately 21 times faster than that reference method on average.