On the Evolutionary Synthesis of Fault-Resilient Digital Circuits

Abstract

In the event of an upset, fault-resilient circuits maintain correct functionality allowing the system to remain fully operational or at least operate with a graceful degradation. Every circuit has a certain level of inherent resilience to faults. Often times, this inherent resilience to faults is insufficient for the given application. This is because conventional synthesis tools generally only focus on optimizing a circuit with respect to area, power, or timing budgets. There is a wide range of applications where faulty circuit behavior can lead to fatal results. Fault injection analyses are reported and show that even a single fault can be critical to the desired circuit operation. To which end, this article presents synthesis of fault-resilient (SYFR) circuits, an evolutionary method for automated synthesis of increased fault-resilience digital circuits suitable for fine-grained use. Test results for synthesis of up to 60 input circuits with SYFR are reported. SYFR can be repeatedly applied to a circuit to obtain various design tradeoffs between fault resilience and implementation costs. SYFR can also be flexibly applied to build circuits, which are selectively fault resilient, i.e., their tolerance to faults is workload aware. In addition, a novel population seeding mechanism to reduce the design space is introduced and experimentally validated. In summary, this article demonstrates that SYFR can be considered a competitive synthesis methodology for constructing fault-resilient circuits.