Input Common Mode Research Articles

FIN-FET BASED HIGH GAIN OP-AMP WITH SLEW RATE ENHANCEMENT IN 45-NM REGIME

In this paper dynamic biasing technique is used for the enhancing the slew rate of the designed Op-Amp. The proposed FinFET based Op-Amp has been verified through Hspice simulator in the standard 45nm Silicon on Insulator FinFET library. The proposed op amp has two stages Miller compensated configuration. A biasing circuit (DSB circuit) is used for dynamic switching of the biasing voltage of the op amp. This leads to lower power consumption, wide ICMR range, and high gain stability. The proposed op amp has a power consumption of 661.83 μW. It has a dual supply voltage of -1.0V and 1.0V. The input common mode range (ICMR) is -800 mV to +900 mV. The Op-Amp has a slew rate of 1.5 KV/μs. Voltage gain of the op amp is 90.4dB. Due to the use of SOI FINFET devices the op amp has relatively less leakage current as compared to similar bulk MOSFET device op amps. The op amp has unity gain bandwidth of 1.27 GHz. Thus, it can be used to transmission and processing of audio and video signals.

A −4–4 V Input Common-Mode Range Bidirectional Current Shunt Monitor

This study describes a novel bidirectional current shunt monitor (CSM) circuit operating at both positive and negative common-mode (CM) voltages. The proposed CSM circuit mainly consists of two comparators, three error amplifiers, several current-mirror transistors and a few resistors. One comparator is used to detect current flowing direction, and the other one is utilized to ensure good operation of CSM circuit with both positive and negative CM voltages. The proposed CSM circuit has been implemented in SMIC 0.18[Formula: see text][Formula: see text]m standard CMOS process and its performances have been verified by simulations. The simulated results show that the proposed CSM circuit, at a supply voltage of 5[Formula: see text]V and with an input CM voltage range from [Formula: see text] to 4[Formula: see text]V, can sense a voltage difference of 4–40[Formula: see text]mV and keep a constant scaled gain of 100[Formula: see text]V/V. The gain error is less than 0.65% and the common-mode rejection ratio (CMRR) is higher than 130[Formula: see text]dB at 1[Formula: see text]kHz. Simulation results show that the output voltage of CSM circuit varies linearly with the CSM input sense voltage.

Differential Electro-Optical Equivalent Circuit Model of a Vertical-Cavity Surface-Emitting Laser for Common-Mode Rejection Ratio Estimation

Vertical-cavity surface-emitting lasers (VCSEL) can be used to achieve galvanic isolation of systems operating in environments with high levels of electromagnetic noise. A small-signal differential electro-optical equivalent circuit model of a VCSEL is presented, in contrast to the usual single-ended models. The electro-optical and opto-electrical conversion of the signal is modelled, as well as the electrical characteristics of the VCSEL chip. The circuit model is based on an approach combining Y-parameters and mixed-mode S-parameters. Compared to conventional models that are aimed at describing the internal laser dynamics, the presented model is primarily focused on modelling the asymmetric parasitics in a differential VCSEL configuration. The parasitics between the 5-lead VCSEL TOSA package and the test printed circuit board are modelled. The impact of the asymmetry of the parasitics from the laser anode and cathode towards the ground is examined. The differential VCSEL model is used to estimate the transfer coefficients for both differential-mode and common-mode input signals. The ratio between the wanted and unwanted signal is expressed as the common-mode rejection ratio (CMRR). The model covers the frequency bandwidth up to 4 GHz required for integrated circuit EMC and ESD measurements.

Low power & high gain differential amplifier using 16 nm FinFET

A low noise, two- stage differential operational amplifiers are designed in 16 nm FinFET technology are presented. The proposed design would be applied in high-speed system on chips (SOCs). The low leakage current, low power dissipation and high current driving abilities of the FinFET are taken into realization with a basic analog building block of OPAMP. In this proposed design dynamic biasing technique is used for enhancing the slew rate of the OPAMP. The input common mode range (ICMR) can be increased and the gain stability is improved by this technique. The performance of a differential amplifier is analyzed using mixed mode device and circuit simulation on FinFET in sub-16-nm node technologies. It observed that by using the FinFET based OPAMP has common mode rejection ratio is 76 dB with improved performance regarding the area, power, and bandwidth. The proposed design has less 1/f noise and better performance that can replace conventional MOSFET in low power Nano circuits.

Systematic Hysteresis Analysis for Dynamic Comparators

Comparator hysteresis is a memory phenomenon allowing outputs maintaining their past stable states until the input difference overcomes a given threshold voltage. In some applications, such as ADCs and memories, hysteresis is a deterministic error that should be minimized. In others, it can be considered as one of the design parameters, such as in implementing hysteresis control-based systems such as peak detectors and spectrum analyzers. In any case, the designer should be aware of how to estimate hysteresis to achieve the desired performances. This paper presents a mathematical approach to estimate hysteresis in clocked latch comparators. It has been demonstrated that hysteresis is not only sensitive to the clock frequency, but also to several design parameters including the transistors sizes, the common mode input voltage and the tracked input frequencies. The analysis results are validated through electrical simulations using a commercially available 0.18[Formula: see text][Formula: see text]m CMOS technology showing a maximum error of 8.6%.

Design Considerations and Development of an Innovative Gate Driver for Medium-Voltage Power Devices With High $dv/dt$

Medium-voltage (MV) silicon carbide (SiC) devices have opened up new areas of applications which were previously dominated by silicon-based IGBTs. From the perspective of a power converter design, the development of MV SiC devices eliminates the need for series connected architectures, control of multilevel converter topologies which are necessary for MV applications, and the inherent reliability issues associated with it. However, when SiC devices are used in these applications, they are exposed to a high peak stress (5–10 kV) and a very high $dv/dt$ (10–100 kV/ $\mu$ s). Using these devices calls for a gate driver with a dc–dc isolation stage that has ultralow coupling capacitance in addition to be able to withstand the high isolation voltage. This paper presents a new MV gate driver design to address these issues while maintaining a minimal footprint for the gate driver. An MV isolation transformer is designed with a low interwinding capacitance, while maintaining the clearance, creepage, as well as insulation standards. A dc isolation test has been performed to validate the integrity of the insulating material. The key features include low input common mode current, and a short-circuit protection scheme specifically designed for 10 kV SiC mosfet s. The performance of the gate driver is evaluated using double pulse tests and continuous tests. Experimental results validate the advantages of the gate driver and its application for MV SiC devices exhibiting very high $dv/dt$ . The proposed gate driver concept is aimed at providing an efficient and reliable method to drive MV SiC devices.

0.5 V Universal Filter Based on Multiple-Input FDDAs

This brief presents a universal filter based on multiple-input fully differential difference amplifier (FDDA) that is suitable for extremely low-power low-voltage applications. The filter employs three FDDAs, eight resistors, four capacitors and can provide low-pass, band-pass, high-pass, band-stop and all-pass voltage responses. Thanks to the utilization of the multiple-input MOS transistor technique, one differential pair with an arbitrary number of inputs is required for constructing the FDDA. Therefore, unlike the previously published FDDA-based universal filters, the proposed filter has the simplest CMOS structure with less power consumption than those already published in the literature. The filter operates with 0.5 V, consumes 740 nW and exhibits rail-to-rail input common mode range. The dynamic range of the BP filter is 73 dB for 1% third intermodulation distortion. The circuit was designed in Cadence/Spectre environment using the TSMC 0.18 µm CMOS process design kit, and the simulation results confirm the advantages of the proposed filter.

Contiguous-Channel Dual-Band Balanced Diplexer

A class of balanced dual-band planar diplexer with frequency-contiguous channels for the differential mode and high common-mode rejection is presented. It exploits double-stub-loaded filtering cells with resistors connected at the symmetry plane of the overall diplexer. In this manner, a sharp-rejection dual-band operation for each diplexer channel with transmission zeroes (TZs) at both sides of the differential-mode dual passbands is obtained. In addition, broadened common-mode suppression and low common-mode in-band input power reflection can be realized. The theoretical foundations and design guidelines for the devised dual-band differential-mode diplexer are provided. Moreover, for practical-validation purposes, a microstrip prototype with imbricated 1.51-GHz/2.41-GHz and 1.92-GHz/2.85-GHz lower and upper dual-band channels is manufactured and tested.

A compact power-efficient 0.5 V fully differential difference amplifier

This brief presents a novel compact CMOS Fully Differential Difference Amplifier (FDDA) structure suitable for extremely low-voltage low-power applications. Unlike the conventional FB-DDAs that employ two differential pairs, the proposed structure employs one differential pair of multiple-input bulk-driven MOS transistor (MI-BD MOST) that results in reduced count of current branches and, consequently, of power consumption. The proposed FDDA has the simplest CMOS structure presented in the literature so far. Furthermore, while the voltage supply is 0.5 V and the power consumption is 246.6 nW the circuit enjoys rail-to-rail input common mode range (ICMR), high common mode rejection ratio (CMRR) of 100.3 dB @ DC, power supply rejection ratio (PSRR) of 127.8 dB@ DC, voltage gain of 61.4 dB and gain bandwidth product of 6.98 kHz for 30 pF capacitive load. The total harmonic distortion (THD) is less than 0.08% for 500 mV/1 kHz input sine wave signal. The circuit was designed and simulated in Cadence/Spectre environment using 0.18 µm CMOS process from TSMC.

Differentially Fed Wideband Circularly Polarized Slot Antenna

This communication presents a novel design of a differentially fed wideband circularly polarized (CP) slot antenna. The CP antenna consists of two opposite-fed C-shaped radiating patches and a stub-loaded corner-truncated rectangular slot. With the slot designed to be antisymmetric with respect to the bisection plane and oppositely fed by two microstrip lines, good differential-mode (DM) performance was obtained. On the other hand, the radiations contributed by the corresponding parts of the antisymmetric CP antenna will be destructive when in common-mode (CM) operation. This results in high CM suppression without a preceding CM-rejection bandpass filter. Also, low DM axial ratios (ARs) were achieved by tuning the truncated corner length, the protruded stub length, and the coupling length and gap of the C-shaped radiating patches. The measurement shows that the designed CP antenna has a wide 10 dB DM impedance band of 5–6.49 GHz and a 3 dB DM AR band of 4.94–6.03 GHz, corresponding to a CP fractional bandwidth of 18.7%. Also, in 4.5–6.5 GHz, the proposed antenna can effectively reject CM input signals because the measured CM return loss is smaller than 2.91 dB, and can convert only very little DM input power into CM reflected power since the DM-to-CM conversion is less than −50 dB.

An ASIC for Recording and Stimulation in Stacked Microchannel Neural Interfaces.

This paper presents an active microchannel neural interface (MNI) using seven stacked application specific integrated circuits (ASICs). The approach provides a solution to the present problem of interconnect density in three-dimensional (3-D) MNIs. The 4 mm2 ASIC is implemented in 0.35 μm high-voltage CMOS technology. Each ASIC is the base for seven microchannels each with three electrodes in a pseudo-tripolar arrangement. Multiplexing allows stimulating or recording from any one of 49 channels, across seven ASICs. Connections to the ASICs are made with a five-line parallel bus. Current controlled biphasic stimulation from 5 to 500 μA has been demonstrated with switching between channels and ASICs. The high-voltage technology gives a compliance of 40V for stimulation, appropriate for the high impedances within microchannels. High frequency biphasic stimulation, up to 40 kHz is achieved, suitable for reversible high frequency nerve blockades. Recording has been demonstrated with mV level signals; common-mode inputs are differentially distorted and limit the CMRR to 40 dB. The ASIC has been used in vitro in conjunction with an oversize (2mm diameter) microchannel in phosphate buffered saline, demonstrating attenuation of interference from outside the microchannel and tripolar recording of signals from within the microchannel. By using five-lines for 49 active microchannels the device overcomes limitations when connecting many electrodes in a 3-D miniaturized nerve interface.

A Low Voltage Bandgap Current Reference with Low Dependence on Process, Power Supply, and Temperature

The minimum power supply voltage of a typical bandgap current reference (BGCR) is limited by operating temperature and input common mode range (ICMR) of a feedback amplifier. A new BGCR using a bandgap voltage generator (BGVG) is proposed to minimize the effect of temperature, supply voltage, and process variation. The BGVG is designed with proportional to absolute temperature (PTAT) characteristic, and a feedback amplifier is designed with weak-inversion transistors for low voltage operation. It is verified with a 0.18-㎛ CMOS process with five corners for MOS transistors and three corners for BJTs. The proposed circuit is superior to other reported current references under temperature variation from -40℃ to 120℃ and power supply variation from 1.2 V to 1.8 V. The total power consumption is 126 ㎼ under the conditions that the power supply voltage is 1.2 V, the output current is 10 ㎂, and the operating temperature is 20℃.

Multiple-input bulk-driven quasi-floating-gate MOS transistor for low-voltage low-power integrated circuits

This brief presents the first experimental results of the multiple-input bulk-driven quasi-floating-gate (MI-BD-QFG) MOS transistor (MOST) which is suitable for low-voltage (LV) low-power (LP) integrated circuits design. The MI-BD-QFG MOST is an extension to the principle of the bulk-driven quasi-floating-gate (BD-QFG) MOST. However, unlike the BD-QFG the MI-BD-QFG MOST offers multiple-input that simplifies specific CMOS topologies and reduce their power consumption. To confirm the advantages of the MI-BD-QFG MOST a Differential Difference Current Conveyor (DDCC) with very simple CMOS structure has been designed and fabricated in a standard n-well 0.18 µm CMOS process from TSMC with total chip area 350 µm × 78 µm. The fabricated circuit uses a 0.5 V power supply, consumes 1.7 µW power and offers near rail-to-rail input common mode range.

A CMOS PFM buck converter employing a digitally programmable voltage level-shifting technique

This paper describes a CMOS pulse frequency modulation (PFM) buck converter employing a digitally programmable voltage level-shifting technique capable of adjusting peak inductor current and output ripple voltage for different load currents. The conventional PFM buck converters employ either an adaptive delay time control circuit or a fixed delay time control circuit to control output ripple voltage and power efficiency with the switching frequency. However, they suffer from a large peak inductor current, resulting in reduced power efficiency. The digitally programmable voltage level-shifting circuit, based on a common source amplifier, is capable of sensing inductor current through the voltage drop caused by on-resistance of the power switch, and can control peak inductor current. The precision needed to control the magnitude of the peak inductor current can be obtained with the number of bits in the digitally programmable voltage level-shifting circuit that are dependent on the input common mode range of the comparator. Employment of one comparator with pre-control logic and post-control logic circuits allows the proposed circuit to improve power efficiency by removing additional circuits, compared with the conventional PFM buck converters. The proposed converter was implemented with a 180 nm CMOS process. The effective chip size of the core block occupies 900μm × 590μm. The proposed PFM mode buck converter with a precision of four bits to control peak inductor current is capable of accommodating an input voltage range of 2.7–3.3 V, and can produce output voltage of 1.2 V. The operational switching frequency measured is on the order of several to several hundred kHz, the load current range is under 150 mA, and the measured output ripple voltage varied, depending on the digital programming status. The measured power efficiency ranged between 70 and 84%.

A Low-Power High-Speed Comparator for Precise Applications

A low-power comparator is presented. pMOS transistors are used at the input of the preamplifier of the comparator as well as the latch stage. Both stages are controlled by a special local clock generator. At the evaluation phase, the latch is activated with a delay to achieve enough preamplification gain and avoid excess power consumption. Meanwhile, small cross-coupled transistors increase the preamplifier gain and decrease the input common mode of the latch to strongly turn on the pMOS transistors (at the latch input) and reduce the delay. Unlike the conventional comparator, the proposed structure let us set the optimum delay for preamplification and avoid excess power consumption. The speed and the power benefits of the comparator were verified using solid analytical derivations, process–VDD–temperature corners, and Monte Carlo simulations along with silicon measurements in $0.18~\mu \text{m}$ . The tests confirm that the proposed circuit reduces the power consumption by 50% and provides 30% better comparison speed at the same offset and almost the same noise budgets. Moreover, the comparator provides a rail-to-rail input $V_{\text {cm}}$ range in $f_{\text {clk}} = 500$ MHz.

A rail‐to‐rail low‐power latch comparator with time domain bulk‐tuned offset cancellation for low‐voltage applications

SummaryLow‐voltage high‐precision comparators are the main building blocks of many low‐power mixed‐mode electronic devices. In this paper, a rail‐to‐rail high‐precision comparator is introduced. The proposed comparator uses 2 parallel input P‐type metal‐oxide‐semiconductor pairs with a dynamic level shifter to ensure rail‐to‐rail operation. Moreover, the proposed circuit incorporates a rail‐to‐rail offset cancellation circuit. The offset cancellation circuit works based on a time domain bulk‐tuned negative feedback loop. The proposed comparator and offset cancellation circuits are designed to work correctly when the input common mode voltage varies from rail to rail. The rail‐to‐rail scheme allows the use of the proposed comparator in nanometer technologies, where the acceptable input range is limited. The proposed circuit was simulated in a standard 180 nm complementary metal‐oxide‐semiconductor technology, and the results proved the rail‐to‐rail comparison ability in addition to the rail‐to‐rail offset cancellation function. The overall power consumption of the comparator was only increased by 11% compared with the conventional non–rail‐to‐rail approach. The maximum clock frequency of the proposed circuit is 833 MHz, which is slightly more than its counterpart at similar operation conditions.

A power efficient charge pump circuit configuration for fast locking PLL application

One of the vital non-linearity issues that exists in a charge pump (CP) circuit is the current mismatch, which does not only reduce efficiency and increases latency, but also generates phase offset while designing a phase locked loop (PLL) thereby leading to large spurious signals. To mitigate such issues, a new charge pump circuit arrangement incorporating miller Op-Amp is proposed in this paper. The circuit simulation is carried out for 90 nm GPDK (Generic Process Design Kit) technology using Cadence Virtuoso platform at a power supply of 1.2 V. The Op-Amp module consumes a power as small as 85.4 µW after offering a moderate gain of 50.71 dB and input common mode range (ICMR) of − 12.16 mV to 1.1 V. The schematic of proposed CP is found to carry an ‘Up’ and ‘Dn’ current of 11.273 and 10.575 µA respectively to read a current mismatch of as tiny as 0.621%, which gets even reduced to 0.616% in post-layout. The vital attributes of the proposed approach are its fast locking time of 31 ns and power dissipation of 134.1 µW only along with a phase noise and reference spur of − 90.21 dBc/Hz @10 MHz offset and − 80.92 dBc/Hz @10 GHz respectively. The performance metrics are also tested under no skew and 5% process skew at different corners for both schematic and post layout cases to prove the variation awareness and robustness of the circuit. The scalability of this configuration is also validated at lower process nodes such as 28 nm UMC.

A novel high CMRR trans-impedance instrumentation amplifier for biomedical applications

A compact high gain current mode instrumentation amplifier (IA) has been proposed for biomedical imaging applications. Conventional IAs rely on several matching resistors which occupies a lot of silicon area, the input and output common mode voltages are exactly same and the maximum applied signal amplitude is limited by internal node voltage swings. The present proposal eliminates the need for matching resistors by processing signals in the current mode. Hence input amplitudes are no longer limited by the voltage headroom and input and output common-mode voltages can be independent. An amplifier with a differential gain greater than 52 dB and a common mode rejection ratio greater than 120 dB has been implemented in 65 nm CMOS Technology and Post layout simulations were presented. The total circuit occupies 4500 μm2 silicon area and circuit consumes ~ 260 μA from 1.8 V power supply.

Overcurrent protection utilising high speed and accurate current sensing circuit for switching mode DC-DC converter

ABSTRACTA high speed and accurate over current protection (OCP) circuit with novel current sensing circuit based on source-degeneration voltage to current converter is presented in this paper for switching mode DC-DC converters. Moreover, a reference generator circuit is designed to generate current set point to be compared with sensed current for OCP. Another four bit binary decoder is employed to control and change the current set point to achieve different levels for OCP. To reduce the fluctuations at the output of the OCP, a blanking-delay block is introduced based on Schmitt trigger topology. The OCP is designed with 130 nm CMOS process technology. Post-layout simulation results show that the OCP works well from 0.5 V to 5 V output voltage of switching mode DC-DC converter. The current sensing block achieves wide input common mode range between 0.5 V and 2.5 V with 61 degree phase margin. OCP works with 3.3 V supply voltage while consuming 600 µA at standby mode and 2 mA when triggering. Total silicon die area is 242 µm × 186 µm.

An Analog Bootstrapped Biosignal Read-Out Circuit With Common-Mode Impedance Two-Electrode Compensation

In this paper, a two-electrode system performing biomedical signal recordings is presented. Thanks to a continuous balancing of the impedance bridge included in the front-end, the proposed system does not suffer the impedance mismatch of a two-electrode front-end that may affect the biopotential measurement. The rejection of the common mode interference has been improved by including a bootstrapped instrumentation amplifier [showing 133 dB common-mode rejection ratio]. The front-end differential input impedance is very high, being in the worst case 500 $\text{M}\Omega $ , whereas its common-mode input impedance is 135 $\text{k}\Omega $ . The proposed architecture also works for an unfavorable input signal-to-noise ratio (SNR) as low as −14 dB. As an example, the electronic interface has been designed and tested for an ECG -like signal. Preliminary tests on a discrete-element electronic prototype have shown the overall system capability of easily recording the heart signal, having evaluated an experimental output SNR of about 32 dB. In addition, the effectiveness of the feedback implementation in restoring the impedance balance has been demonstrated in practice.