Input Circuit Research Articles

Systems and Circuits Linking Chronic Pain and Circadian Rhythms.

Research over the last 20 years regarding the link between circadian rhythms and chronic pain pathology has suggested interconnected mechanisms that are not fully understood. Strong evidence for a bidirectional relationship between circadian function and pain has been revealed through inflammatory and immune studies as well as neuropathic ones. However, one limitation of many of these studies is a focus on only a few molecules or cell types, often within only one region of the brain or spinal cord, rather than systems-level interactions. To address this, our review will examine the circadian system as a whole, from the intracellular genetic machinery that controls its timing mechanism to its input and output circuits, and how chronic pain, whether inflammatory or neuropathic, may mediate or be driven by changes in these processes. We will investigate how rhythms of circadian clock gene expression and behavior, immune cells, cytokines, chemokines, intracellular signaling, and glial cells affect and are affected by chronic pain in animal models and human pathologies. We will also discuss key areas in both circadian rhythms and chronic pain that are sexually dimorphic. Understanding the overlapping mechanisms and complex interplay between pain and circadian mediators, the various nuclei they affect, and how they differ between sexes, will be crucial to move forward in developing treatments for chronic pain and for determining how and when they will achieve their maximum efficacy.

Integrated 10-GHz Graphene FET Amplifier

Graphene has unique electrical and mechanical properties which can pave the way for new types of devices for microwave applications. However, emerging technologies often have problems with yield and still considerable variation in device parameters cause great challenges for circuit design. In this paper, we present the design and development of an integrated graphene FET amplifier addressing this challenge. A representative graphene FET was selected from a set of devices and then the input and output matching circuits were designed using the negative-image technique. The two-finger GFET with a gate length of 0.5 μm exhibit a typical f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> of 35 GHz and 37 GHz, respectively. The integrated graphene FET amplifier was fabricated on a high-resistivity silicon substrate together with thin film capacitors, airbridges, and spiral inductors. A record high gain of 4.2dB at 10.6GHz was measured for a single transistor amplifier stage and agrees well with simulations. These results indicate significant progress towards active microwave circuits based on emerging 2D materials.

Lookup table‐based negative‐bias temperature instability effect and leakage power co‐optimization using genetic algorithm approach

SummaryAs a result of continuous scaling of transistors, negative bias temperature instability (NBTI) has become a serious reliability concern which causes the device to degrade over its lifetime. Similarly, leakage power also remains a key issue in deep submicron technologies. Both NBTI‐related delay degradation and standby time leakage power depend strongly on the circuit's input patterns. The input vector control (IVC) technique can be used for mitigating both NBTI‐related delay degradation and leakage power. However, the input vectors with the least NBTI‐induced degradation may not be the same ones with the least leakage power in any circuit; therefore, co‐optimization is needed to minimize leakage and NBTI‐induced degradation. In this paper, a genetic algorithm (GA)‐based approach is presented to co‐optimize both NBTI‐related performance degradation and also leakage power. We are also presenting a trade‐off analysis by giving different weightage to the NBTI effect and leakage power. Simulation results applied on ISCAS'85 benchmark circuits illustrate that on average our proposed technique saves up to 21.85% and 17.68% circuit performance degradation and the leakage power, respectively.

Vehicle tracking algorithm based on deep learning

Vehicle detection is one of the most important detection targets in target detection. overcoming this problem is of great significance in the field of traffic detection and automatic driving. In this paper, based on yolov4, firstly, the slice module is added to the input, and the silce module slices the image into the backbone to get the sampling feature map without information loss. Then, the SPP module is added to the neck of neck module, and then the Kitti dataset is trained, detected and tested. Experiments show that adding slice module in the input circuit and spp module in the neck can effectively improve the accuracy of vehicle detection Map@0.5 3.4%.

The determination of redundant test patterns based on binary matrix symmetry properties

The object of research are digital circuit control tests. The model of a digital circuit is of a grey-box type. Test patterns (impacts) are combinations of logical zeros and ones, applied to circuit inputs. A binary matrix is the response of a digital circuit to input impacts. The examined faults are of «bridging faults» and «stuck-at faults» types. We distinguish the structural units of a test, as well as transformations, maintaining its structure. The measure of binary matrix symmetry is defined. Based on the measure obtained, the criteria are introduced, which help to calculate the utility of another test impact upon a digital circuit. To investigate the criteria, both pseudo-random and deterministic test sequences have been used. Among others, we have observed such algorithmic sequences as a sliding-ONE test, a logarithmic test, a galloping test pattern and a checkerboard test. The proposed approach gives the possibility to identify and exclude the impacts, not carrying useful information, from a test of combinational circuit control. The developed criteria can also be applied to construct memory tests. The analysis of experimental data allows us to make a conclusion about the advisability of using the proposed mathematical apparatus in the theory and practice of digital device testing, as well as in processes of test development.

Analysis on the Performance of a Second-order and a Third-order RLC Circuit of PRBS Generator

A pseudo-binary random signal (PRBS) has been widely utilized for system identification in complex signals to develop an experimental approach. PRBS generator is a circuit that generates pseudo-random numbers. This work aims to analyze the best fit value of the PRBS generator with second-order and third-order under-damped black-box RLC circuit of the estimated model. The procedures conducting here can be divided into three parts. First, to design two black boxes using the RLC circuit representing a critically under-damped second-order and third-order system. PRBS generated with maximum-length sequence (MLS) equals 127 bits by using seven shift registers. Second, simulate the PRBS generator using MATLAB software and validate the estimated model from the simulation using the System Identification Tool in MATLAB. Next, connecting hardware RLC circuit and reading input and output signals using an oscilloscope. Finally, 2500 samples of captured data were used for estimation. Then, analyze and compare the best fit of the simulation and experiment with second-order and third-order under-damped black-box RLC circuit. Furthermore, analyze and compare best fit using different sample time. The results showed that the best fit of the second-order model with under-damped black-box RLC circuit was autoregressive with the exogenous term (ARX) 211, where the best fit of the simulation was 99.88%, and the best fit of the experiment was 96.04%. And the results showed that the best fit of the third-order model with an under-damped black-box RLC circuit was ARX 331, where the best fit of the simulation was 99%, and the best fit of the experiment was 94.28%. It was concluded that the best fit value of the second-order was better than the third order. What’s more, the results showed that when the select range is the same, the bigger the sample time, the better the best fit.

Topology of non-inductive DC/DC converters with galvanic isolated circuits

Non-inductive (throttle-free) DC/DC converters are used in low-power and highly integrated electronic systems. A circuit analysis of the basic topologies of non-inductive DC/DC charge-pumped converters which perform typical DC-voltage conversions, i.e., lowering, raising and inverting, was carried out. The galvanic isolation between the input and output circuits of the converter was achieved even in the integrated version due to forming a time delay of the switches (Dead Time, DT), commuting a “flying” capacitor, which is transferring the charge to the storage capacitor and the load. A circuit of the DT driver was developed and its parameters, at which the through-current flow in the switch is prevented and the conditions of galvanic isolation of the input and output circuits are satisfied, were studied. The simulation was built with a popular Electronics Workbench software, widely used in training of specialists in radio electronics at higher educational institutions. The results of the study of the basic power characteristics of DC/DC conversion, such as output current and voltage, voltage transfer coefficient, efficiency, output equivalent resistance, were presented. The efficiency of conversion was estimated by varying the capacities of the “flying” and storage capacitors, the resistance of the switches in the closed state, and the frequency of switching. It is proved that the charge pumping method is simple and effective at low load currents (mA units), when both the voltage transfer coefficient from input to output and efficiency are high, and are approaching to “one”. However, with the increase of the load current, the voltage transfer coefficient and efficiency decrease, the output voltage ripples increase.

Long Short-Term Memory Neural Networks for Modeling Nonlinear Electronic Components

This article presents a new macromodeling approach for nonlinear electronic components and circuits based on long short-term memory (LSTM) neural network. LSTM proposes a more efficient training process in comparison with the conventional recurrent neural network (RNN) training. Conventional structures such as RNN suffer from the gradient vanishing problem during the training process. LSTM addresses this issue and solves this problem in an efficient way. In order to train the proposed structure, some input and output waveforms of the original circuit, called training waveforms, should be obtained from simulation tools or measurements. Model creation using proposed method does not require information on details inside the components and input-output training waveforms are sufficient to construct the model. The provided numerical results in this article show that the proposed method is more efficient than RNN techniques for modeling components and packages in terms of both speed and accuracy. The findings suggest that the proposed method significantly reduces the training time in comparison with conventional state-of-art modeling techniques. Furthermore, simulation time of the obtained model from the proposed technique is less than both conventional models (such as SPICE models) used in circuit simulation tools and models obtained from conventional RNN method. Three practical examples, namely, an audio amplifier, Texas Instruments (TIs) SN74AHCT540 device, and MOS inverter, are utilized to manifest the validity of the proposed macromodeling approach.

An improved sliding-mode observer-based equivalent-input-disturbance approach for permanent magnet synchronous motor drives with faults in current measurement circuits

The reliability of permanent magnet synchronous motor (PMSM) systems is very important in high-precision industrial drives. However, disturbance or sensor fault may cause the performance degradation of the system. This paper presents an improved sliding-mode-observer (SMO)-based equivalent-input-disturbance (EID) approach for the rejection of faults in current measurement circuits of a PMSM drive. A system model, which contains faults in current measurement circuits, is first constructed by using EIDs in control input circuits. Then, an improved SMO is designed to estimate the equivalent-input-faults. The effect of the faults on the system is rejected based on the EID theory. Moreover, the global stability and convergence analysis is also provided. Experiments and comparisons demonstrate the effectiveness of the method.

Masking Circuit Faults and Trojan Circuit Injections Using Sat Solvers

Combinational circuit C composed of gates and its sub-circuit with set V of output nodes and set U of input nodes are considered. The set V consists of output nodes of fault gates of the circuit C (only logical faults are examined) and fault free gates, the inputs of which are at the same time lines in that Trojan circuit payloads are injected. A procedure of forming the set U, as a rule, depends on circuit C fabrication technology and is out of our consideration. We suggest recovering the circuit C behavior by using as much as possible simple masking circuits (patch circuits). Masking circuit inputs are connected with nodes from the set U, and outputs are united either with nodes that are fed by nodes from the set V or directly with nodes from the set V. The conventional way of recovering the circuit C behavior (in the frame of Engineering Change Order (ECO) technologies) is based on using results of circuit C simulation. This way guarantees correct circuit C behavior only on a set of Boolean vectors applied during simulation. We suggest using incompletely specified Boolean functions of nodes from V in the frame of ECO technologies, which allows guaranteeing correct behavior of the circuit C among all its input Boolean vectors. Deriving the incompletely specified Boolean functions is connected with applying SAT solvers. Having got these functions, we then obtain the masking circuit (patch circuit) using ESPRESSO and ABC systems.

SIMULATION OF AN ELECTROMYOGRAPHIC SIGNAL CONVERTER FOR ADAPTIVE ELECTRICAL STIMULATION TASKS

The subject matter of the article is an electromyographic signal transducer, which are an integral part of devices for adaptive electrical stimulation of muscle structures based on reverse electromyographic communication. The goal of the work is to study the features, obtaining the corresponding theoretical relationships and computer modeling of a differential biopotential converter, providing amplification of the useful component and suppression of harmful interference, the spectra of which intersect. The following tasks were solved in the article: determining the effect of electrode width and electrode spacing on crosstalk; formation of the electrode-skin model and the input circuit of the transducer, obtaining theoretical relations for calculating the rejection coefficient, construction of the transducer circuit and its computer simulation. The following methods were used – methods of mathematical modeling of processes and technical devices; methods of analysis, structural and parametric synthesis of nonlinear electronic circuits; methods of machine design. The following results were obtained – a biopotential amplifier circuit with tracking feedback on power supply is proposed; modeling of dynamic processes by means of the Multisim program was carried out; on the basis of the constructed model of the electrode-skin input circuit and the obtained analytical relationships, the rejection coefficient of the input circuit of the equivalent circuit is calculated; the requirements for the signal registration module are formulated. Conclusions: The considered version of the electromyographic signal converter circuit based on tracking communication on power supply, effectively rejects 50 Hz common mode noise. On the basis of the constructed equivalent model of the input circuit of the amplifier, the theoretical relation for calculating the rejection coefficient of such amplifiers. The circuit is simulated in the Multisim program, the results confirmed the correctness of its functioning. The requirements for the interelectrode distance and the thickness of the electrodes themselves are also formulated. The results obtained can be used to design complexes for adaptive electrical stimulation.

Adaptive Spatial Hybrid Nulling of Extremely Strong Interfering Signals

This article describes and examines a method of spatial suppression of extremely strong interfering signals (ISs) capable of complete desensitization and even damage of victim receivers’ input circuits. This method not only protects victim receivers but also allows them to reliably receive desired signals in the presence of such ISs, using adaptive hybrid nulling whose first stage is performed at the receivers’ analog inputs and the second stage is carried out in the receivers’ digital portions.

Test Generation for Hardware Trojan Detection Using Correlation Analysis and Genetic Algorithm

Hardware Trojan (HT) is a major threat to the security of integrated circuits (ICs). Among various HT detection approaches, side channel analysis (SCA)-based methods have been extensively studied. SCA-based methods try to detect HTs by comparing side channel signatures from circuits under test with those from trusted golden references. The pre-condition for SCA-based HT detection to work is that the testers can collect extra signatures/anomalies introduced by activated HTs. Thus, activation of HTs and amplification of the differences between circuits under test and golden references are the keys to SCA-based HT detection methods. Test vectors are of great importance to the activation of HTs, but existing test generation methods have two major limitations. First, the number of test vectors required to trigger HTs is quite large. Second, the HT circuit’s activities are marginal compared with the whole circuit’s activities. In this article, we propose an optimized test generation methodology to assist SCA-based HT detection. Considering the HTs’ inherent surreptitious nature, inactive nodes with low transition probability are more likely to be selected as HT trigger nodes. Therefore, the correlations between circuit inputs and inactive nodes are first exploited to activate HTs. Then a test reordering process based on the genetic algorithm (GA) is implemented to increase the proportion of the HT circuit’s activities to the whole circuit’s activities. Experiments on 10 selected ISCAS benchmarks, wb_conmax benchmark, and b17 benchmark demonstrate that the number of test vectors required to trigger HTs reduces 28.8% on average compared with the result of MERO and MERS methods. After the test vector reordering process, the proportion of the HT circuit’s activities to the whole circuit’s activities is improved by 95% on average, compared with the result of MERS method.

Exploratory Designing a Magnetic Induction Tomography Sensor Coil Circuit for Agarwood

Magnetic induction tomography (MIT) is an imaging modality focused on tracing the transmission of electrical conductivity within the body. This technique used to image electromagnetic properties of an object by using the eddy current effect. This paper explains the primary analog transceiver circuit of MIT. This is a surrogate design of the analog system in the electronic components for pattern recognition and conditioning. This MIT system operating with a single excitation signal frequency at 10MHz. The input voltage received by the receiver sensor would become the circuit input which contained information. The four stages process in the receiver circuit successfully captured the signal from the transmitter. These subsystems have their functions and can be put into effect in many ways. Therefore, the circuit was used to be reliable at agarwood samples. The approach transceiver circuit were successful and functional for MIT coil sensing. The input voltage feedback depending on the conductivity of the samples. As the dielectric properties of samples are high, the input voltage at the receiver also high. Therefore, 10MHz can use for agriculture while this range of frequency is usually used in biomedical applications. Series – parallel circuit gives a greater induction factor and therefore more induced voltage for the load of the receiver.

Nonlinear convergence boosts information coding in circuits with parallel outputs

Neural circuits are structured with layers of converging and diverging connectivity and selectivity-inducing nonlinearities at neurons and synapses. These components have the potential to hamper an accurate encoding of the circuit inputs. Past computational studies have optimized the nonlinearities of single neurons, or connection weights in networks, to maximize encoded information, but have not grappled with the simultaneous impact of convergent circuit structure and nonlinear response functions for efficient coding. Our approach is to compare model circuits with different combinations of convergence, divergence, and nonlinear neurons to discover how interactions between these components affect coding efficiency. We find that a convergent circuit with divergent parallel pathways can encode more information with nonlinear subunits than with linear subunits, despite the compressive loss induced by the convergence and the nonlinearities when considered separately.

A high voltage pulse generator using avalanche‐mode thyristors

AbstractA high voltage and high current pulse switch using avalanche mode thyristor has been developed for the high voltage pulse generator. When the break‐over voltage is applied to a thyristor, the thyristor turns on without the gate input current. We call avalanche mode thyristor (AMT) which operates such a switch mode. AMT has many advantages, for example, turn on function without trigger input circuit in the series connection, high speed switching characteristics, etc. A magnetic switch (MS) using the saturation of the core is adopted for the high current pulse shaping. Twelve stages of AMTs generate 11 kV and 1.36 kA with 260 nanoseconds pulse width. A high voltage pulse has been produced up to 65 kV, 43A by using the AMT pulse generator and a pulse trans. The behavior of AMT and the performance of the circuit are discussed.

Approximate Logic Synthesis Using Boolean Matrix Factorization

Approximate computing is an emerging computing paradigm offering benefits in hardware metrics, such as design area and power consumption, by relaxing the requirement for full accuracy. In circuit design, a major challenge is to synthesize approximate circuits automatically from input exact circuits requiring minimal expert input. In this work, we present a method for approximate logic synthesis based on the Boolean matrix factorization, where an arbitrary input circuit can be approximated in a controlled fashion. Our methodology enables automatic computation of the dominant elements, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bases</i> , of the truth table of the circuit, and later combines the bases to approximate the original truth table. Such compression can reduce the complexity of the hardware implementation significantly, while introducing variable degrees of inaccuracy. Furthermore, in our approach, the factorization algorithm can be fine tuned as required by the application, to effectively improve control over degree of approximation. In this work, we provide a unified approach enabling the factorization algorithm to utilize semiring algebra, field algebra, and a combination of both for truth table factorization. In addition, we provide an automatic circuit partitioning approach and a design space exploration heuristic to navigate the search space. We implement our methodology using a full stack of open-source tools, and thoroughly evaluate our methodology on a number of representative circuits showcasing the benefits of our proposed methodology for approximate logic synthesis. Finally, we compare our methodology against an existing library of approximate designs and demonstrate state-of-the-art performance.

R -Simple k -Path and Related Problems Parameterized by k / r

Abasi et al. (2014) introduced the following two problems. In the r -S imple k -P ath problem, given a digraph G on n vertices and positive integers r , k , decide whether G has an r -simple k -path, which is a walk where every vertex occurs at most r times and the total number of vertex occurrences is k . In the ( r , k )-M onomial D etection problem, given an arithmetic circuit that succinctly encodes some polynomial P on n variables and positive integers k , r , decide whether P has a monomial of total degree k where the degree of each variable is at most r . Abasi et al. obtained randomized algorithms of running time 4 ( k / r )log r ⋅ n O (1) for both problems. Gabizon et al. (2015) designed deterministic 2 O (( k / r )log r ) ⋅ n O (1) -time algorithms for both problems (however, for the ( r , k )-M onomial D etection problem the input circuit is restricted to be non-canceling). Gabizon et al. also studied the following problem. In the P -S et ( r , q )-P acking P roblem , given a universe V , positive integers ( p , q , r ), and a collection H of sets of size P whose elements belong to V , decide whether there exists a subcollection H ′ of H of size q where each element occurs in at most r sets of H ′ . Gabizon et al. obtained a deterministic 2 O (( pq / r )log r ) ⋅ n O (1) -time algorithm for P -S et ( r , q )-P acking . The above results prove that the three problems are single-exponentially fixed-parameter tractable (FPT) parameterized by the product of two parameters, that is, k / r and log r , where k = pq for P -S et ( r , q )-P acking . Abasi et al. and Gabizon et al. asked whether the log r factor in the exponent can be avoided. Bonamy et al. (2017) answered the question for ( r , k )-M onomial D etection by proving that unless the Exponential Time Hypothesis (ETH) fails there is no 2 o (( k / r ) log r ) ⋅ ( n + log k ) O (1) -time algorithm for ( r , k )-M onomial D etection , i.e., ( r , k )-M onomial D etection is unlikely to be single-exponentially FPT when parameterized by k / r alone. The question remains open for r -S imple k -P ath and P -S et ( r , q )-P acking . We consider the question from a wider perspective: are the above problems FPT when parameterized by k / r only, i.e., whether there exists a computable function f such that the problems admit a f ( k / r )( n +log k ) O (1) -time algorithm? Since r can be substantially larger than the input size, the algorithms of Abasi et al. and Gabizon et al. do not even show that any of these three problems is in XP parameterized by k / r alone. We resolve the wider question by (a) obtaining a 2 O (( k / r ) 2 log( k / r )) ⋅ ( n + log k ) O (1) -time algorithm for r -S imple k -P ath on digraphs and a 2 O ( k / r ) &amp;sdot ( n + log k ) O (1) -time algorithm for r -S imple k -P ath on undirected graphs (i.e., for undirected graphs, we answer the original question in affirmative), (b) showing that P -S et ( r , q )-P acking is FPT (in contrast, we prove that P -M ultiset ( r , q )-P acking is W[1]-hard), and (c) proving that ( r , k )-M onomial D etection is para-NP-hard even if only two distinct variables are in polynomial P and the circuit is non-canceling. For the special case of ( r , k )-M onomial D etection where k is polynomially bounded by the input size (which is in XP), we show W[1]-hardness. Along the way to solve P -S et ( r , q )-P acking , we obtain a polynomial kernel for any fixed P , which resolves a question posed by Gabizon et al. regarding the existence of polynomial kernels for problems with relaxed disjointness constraints. All our algorithms are deterministic.

A Light-Driven Vibrotactile Actuator with a Polymer Bimorph Film for Localized Haptic Rendering.

A vibrotactile actuator driven by light energy is developed to produce dynamic stimulations for haptic rendering on a thin-film structure. The actuator is constructed by adopting a thermal bimorph membrane structure of poly(3,4-ethylenedioxythiophene) doped with p-toluenesulfonate (PEDOT-Tos) coated onto a polyethylene terephthalate (PET) film. Upon irradiation of near-infrared (NIR) light, the light energy absorbed at the PEDOT-Tos layer is converted into thermoelastic bending deformation due to the mismatch in coefficient of thermal expansion between PEDOT-Tos and PET. Since the light-induced deformation is reversible, spatially localized, and rapidly controllable with designed light signals, the proposed actuator can produce vibrotactile stimulation over 10 dB at arbitrary areas in the human-sensitive frequency range from 125 to 300 Hz using a low input power of ∼2.6 mW mm-2, as compared with a complex electrical circuit and high input power needed to achieve such actuation performance. Together with its simple structure based on light-driven actuation, the advent of this actuator could open up new ways to achieve substantial advances in rendering textures at a flexible touch interface.

A characteristic standardization method for circuit input vectors based on Hash algorithm

The lengths of input vectors corresponding to different circuits are often quite different, which makes it difficult to standardize them. This paper proposes a characteristic standardization method for circuit input vectors based on hash algorithm. First, the collision rates of different hash algorithms are analyzed, and four representative hash algorithms are selected to process the input vectors. Then, based on the given dataset, their performance is analyzed from collision rate, stability and distribution characteristics, and the best performing RSHash algorithm is selected for further research. Next, we deal with the input vectors using RSHash mapping and partitioning strategy, respectively, and then apply processed input vectors to the deep autoencoder network to perform experiments. The experimental results show that the characteristic standardization method for circuit input vectors based on RSHash algorithm has better performance.