Input Bus Research Articles

Half-bridge inverter using 4H-SiC gate turn-off thyristors

This paper reports on the first demonstration of a half-bridge power inverter constructed from silicon carbide gate turn-off thyristors (GTOs) operated in the conventional GTO mode. This circuit was characterized with input bus voltages of up to 600 VDC and 2 A (peak current density of 540 A/cm/sup 2/) with resistive loads using a pulse-width modulated switching frequency of 2 kHz. We discuss the implications of the thyristor's electrical characteristics and the circuit topology on the overall operation of the half-bridge circuit. This work has determined the conservative critical rate of rise value of the off-state voltage to be 200 V//spl mu/s in these devices.

Vertically coupled glass microring resonator channel dropping filters

Air-clad glass microring resonators vertically coupled to buried channel waveguides are experimentally investigated. Ring radii of 10 μm, and channel drop bandwidths of 5 nm are reported. Vertical coupling eliminates the need for the etching of fine features, and relaxes the alignment of the resonator with respect to the input and output bus waveguides.

Analysis, design, and experimental results of a 1-kW ZVS-FB-PWM converter employing magamp secondary-side control

The design and breadboard implementation of a constant-frequency, zero-voltage-switched, full-bridge pulsewidth modulation converter delivering a 12-V-at-1-kW output from a 350-450-VDC input bus is described. The zero-voltage switching characteristic is maintained over a wide operating range by utilizing the transformer magnetizing inductance as an energy storage element. Output voltage regulation is accomplished entirely on the secondary side through magamp control, thus simplifying the methods used for maintaining control and isolation.

Sound synthesis model incorporating sympathetic vibration of strings

Synthesizer models for emulating musical instruments are improved to take into account sympathetic string vibrations. One embodiment of the present invention scales an output signal from a sound synthesis model (220) and uses the scaled signal as an input signal for a number of single-string emulators (201-212) causing the single-string emulators to produce sound signals corresponding to sympathetic string vibrations. The output signals from the synthesis model (220) and from all of the single-string emulators (201-212) are added together. Another embodiment employs an octave's worth of single-string emulators to emulate the lower strings of an emulated instrument. Still another embodiment is a synthesizer which includes an input bus (220A) for accepting a sound signal, scaling means (244), a plurality of single-string emulators, and means for summing output signals from the string emulators. Embodiments preferably employ waveguide synthesis or the plucked string model to emulate single strings.

A fine-grained Ethernet performance model

We have developed a novel analytical Ethernet performance model that contains a complete formulation of system response time from the initiation of user requests for service to the delivery of the service to the user. The estimated response time includes simultaneous input bus delay (requests for service from multiple users), simultaneous output delay (responses to requests from multiple servers), considering time lost to collisions and subsequent backoff time, time lost to deferring transmission due to a busy channel, and transmission time. In addition, we include server disk input and output queueing times and server and user disk access times. By modeling all epochs of collision, backoff, and transmission events, we have developed a way of providing a level of detail and accuracy that other analytic models of Ethernet performance do not provide. In addition to using the model for estimating response time as a function of number of users and servers, the model is used to determine the number of servers that would be appropriate for a given range of number of users.

A modular multirate video distribution system-design and dimensioning

A modular architecture is proposed for distributing broadcast and switched video. The architecture consists of a set of concentration buses (or input buses), a TDM-based bus matrix and a set of distribution buses (or output buses). The transmission time in each output bus is divided into fixed size frames. Dedicated time slots in a frame are reserved for broadcast video. The remaining time slots are allocated to switched video on a first-come-first-served basis. Videos are switched via time slot assignments which determine the connections within the bus matrix. Two slot assignment algorithms are designed, one for point-to-point transmissions and the other for point-to-multipoint transmissions. The advantages of this architecture include: (1) accommodation of multirate video, (2) support of video broadcasting and multicasting, and (3) modular growth at distributed locations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Microcode simulator for Apple Macintosh

No fewer than three microcode simulators have been described in this bulletin since 1987. Carlson's [1] runs on an IBM mainframe, Donaldson's [3] on DOS machines and Dunworth's [4] on DOS or unix machines. All have a traditional textual interface. We wanted a visual interface that would display a circuit diagram (figure 1) and let a user follow the execution of a microprogram by watching the action of the gates. The first version became operational in the fall of 1990 and has survived two academic years of use by undergraduates.Microcode has traditionally been written using an obtuse mnemonic with such instructions as "a=7, b=3, ab, add, ramf, mar=y". We did not want students to have to contend with that kind of syntax, so our users write microcode by responding to a series of dialogs . The user makes a choice either by the "point and click" technique or by typing a keystroke equivalent. For example, the keystroke corresponding to the addition operation is "+".When the input #1 dialog comes up, the user can put register 7 on input bus "a" by typing "7". Keystrokes are buffered, allowing "power programmers" to type as fast as they wish. The dialogs can keep up with most programmers on any of the various Mac-II models. Even on the slower Mac SE, the standard sequence of eight dialogues can be completed in approximately four seconds, which is considerably less time than it takes to flawlessly type "a=7, b=3, ab, add, ramf, mar=y". After two years of field testing, several improvements suggested by students have been incorporated into the editor. Students, with the exceptions of a few intransigent DOS zealots, are now generally satisfied with the operation of the microcode editor.

An enhanced LQ adaptive VAr unit controller for power system damping

Static VAR compensators have been installed in power systems primarily to function in the steady state regulation of voltage levels or reactive power flows. More recently however there has been much interest in utilizing these devices to improve the dynamic performance of power systems. This paper presents an adaptive linear quadratic Gaussian control strategy for static var systems to enhance power system damping and stability. The control strategy uses only local information to dampen oscillatory modes present in the network. The controller calculates an appropriate value of VAr unit susceptance to present to the network at each sampling instant. The calculation of the appropriate susceptance value is based on a reduced-order model of the power system which is obtained on-line by a least squares identification procedure. The controller consists of three main components: an identifier, an adaptive observer, adn an adaptive LQG regulator. The identifier users a recursive least squares type of algorithm to fit a linear, discrete transfer function model to a sequence of input and output signals obtained from the power system. This results in a reduced-order approximation to the actual power system. For this study, VAr unit susceptance is used as the input signal and bus frequency deviation is used as the output signal. The coefficients of the identified transfer function are then sent to both the adaptive observer and the adaptive regulator. The observer is an observable-cannonical representation of the system and it calculates a state vector representing system dynamics.

An Enhanced LQ Adaptive VAR Unit Controller for Power System Damping

Static VAR compensators have been installed in power systems primarily to function in the steady state regulation of voltage levels or reactive power flows. More recently however there has been much interest in utilizing these devices to improve the dynamic performance of power systems. This paper presents an adaptive linear quadratic Gaussian control strategy for static var systems to enhance power system damping and stability. The control strategy uses only local information to dampen oscillatory modes present in the network. The controller calculates an appropriate value of VAr unit susceptance to present to the network at each sampling instant. The calculation of the appropriate susceptance value is based on a reduced-order model of the power system which is obtained on-line by a least squares identification procedure. The controller consists of three main components: an identifier, an adaptive observer, adn an adaptive LQG regulator. The identifier users a recursive least squares type of algorithm to fit a linear, discrete transfer function model to a sequence of input and output signals obtained from the power system. This results in a reduced-order approximation to the actual power system. For this study, VAr unit susceptance is used as the input signal and bus frequency deviation is used as the output signal. The coefficients of the identified transfer function are then sent to both the adaptive observer and the adaptive regulator. The observer is an observable-cannonical representation of the system and it calculates a state vector representing system dynamics.

A real-time video signal processor suitable for motion picture coding applications

A real-time video signal processor (VSP) system has been developed. The system employs three multiprocessor clusters, each of which has 12 video signal processor modules (VSPMs). A VSPM in a cluster processes its assigned subimage by using an overlap-save technique. Each cluster uses the same multiprocessor structure, in which homogeneous processor modules are connected to input, output, and feedback buses in parallel and two bus switch units. By controlling these units, the clusters can be combined in pipeline and/or parallel forms. Each cluster also uses a variable delay unit which achieves up to one frame delay on the feedback bus. By using this unit, interframe processing can be carried out without using internal data memories in VSPMs for the frame delay. The employment of the bus switches and the variable delay unit increases flexibility for a variety of signal processing algorithms. The system performs 500 million operations per second and is currently used as a real-time evaluation system for low-bit-rate picture encoders. >

ESD protection: design and layout issues for VLSI circuits

The electrostatic discharge (ESD) design issues for input, output, and power bus protection of metal-oxide semiconductor very-large-scale integration (VLSI) devices are reviewed. For input pins, the critical layout techniques that determine primary and secondary protection circuits are reported. For output pins, the effective use of the output buffer itself as a protection circuit is discussed. An effective primary circuit for rapidly discharging large amounts of stress current is a thick-oxide device with optimized layout. This device with a grounded source diffusion can provide up to 6 kV of ESD protection for the human body stress model. Some of the recent advanced process features for enhancement of VLSI circuit reliability are presented, as well as their impact on the protection circuit design and layout.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

HIDRA: a hierarchical instrument for distributed real-time analysis of biological signals.

This work presents a locally distributed common bus multiple-processor system intended to support a hierarchical signal processing scheme for biological signal analysis. Each peripheral unit-the so called preprocessor (PP)-executes real-time signal processsing algorithms over data multiplexed in an input bus. The result of this analysis is transferred to a host computer that integrates the received information from the PP's, saves it in disk when necessary, performs higher level data analysis, and interfaces to the user. The processing of electroencelographic (EEG) data will be used as a case study, due to the multidimensional aspects involved.

Preliminary results from the multishot opening switch and barrel testing at ARDC

The General Electric (GE) Multishot Switch and Barrel have been designed and assembled, and preliminary testing has been carried out at the Armament Research and Development Center (ARDC) at Dover, NJ. The Electromagnetic Launcher System incorporates an existing homopolar generator, storage inductor, and range tank with the GE switch and barrel into a Multishot Facility capable of three 500 kA shots at a rate of 4 Hz. Preliminary low current (∼250 kA) single shot tests of the system indicate that the Multishot injector, data acquisition and control systems, and shot timing meet design objectives and that the switch does commutate effectively into a moving armature at an arc voltage of 335 volts. Five single shot tests have been performed on the system. In these tests the switch brush has experienced difficulty in carrying full charge current (>300 kA) in the opening segment of the switch. Static measurement of contact voltage on the stationary brush at 60 Hz, 450 kA has eliminated contact resistance runaway as a possible cause of this difficulty. Deflection measurement in situ at ARDC, using 300 kA in a short circuit test and 3-D finite element analysis of the magnetic force on the brush suggest a possible loss of contact between brush fingers and switch rail surfaces, particularly in the periphery of the input bus. Increased compliance is being built into the brush and the switch assembly is being widened to accommodate the wider brush. Full power switch testing is underway to evaluate the effectiveness of these design changes, and Multishot testing is scheduled to resume when the ARDC facility again becomes available. The Multishot Electromaqnetic Gun Program was developed under Air force Armament Laboratory sponsorship.

Color Video Switching

In color video switching equipment, the nature of the encoded signal requires that particular care be taken to achieve, over the frequency band, constant amplitude and delay, low differential gain and phase, and low crosstalk. Furthermore, performance must be independent of the number of output circuits connected to a particular input bus. Equipment meeting these requirements has been operating in CBS color-television studios in New York and Hollywood since August 1954. The objectives were achieved by adding back-contact loading to maintain constant capacitance on each input bus, by compensating this capacitance with loading coils in each input bus, by reducing capacitance coupling through contacts, and by minimizing distortion in output coupling amplifiers.