ESD protection: design and layout issues for VLSI circuits

Abstract

The electrostatic discharge (ESD) design issues for input, output, and power bus protection of metal-oxide semiconductor very-large-scale integration (VLSI) devices are reviewed. For input pins, the critical layout techniques that determine primary and secondary protection circuits are reported. For output pins, the effective use of the output buffer itself as a protection circuit is discussed. An effective primary circuit for rapidly discharging large amounts of stress current is a thick-oxide device with optimized layout. This device with a grounded source diffusion can provide up to 6 kV of ESD protection for the human body stress model. Some of the recent advanced process features for enhancement of VLSI circuit reliability are presented, as well as their impact on the protection circuit design and layout.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>