InP HBTs Research Articles

A Knowledge-Guided Neural Network-Based Large-Signal Model for InP HBTs With Self-Heating Effect Consideration

A Knowledge-Guided Neural Network-Based Large-Signal Model for InP HBTs With Self-Heating Effect Consideration

Model Parameters and Degradation Mechanism Analysis of Indium Phosphide Hetero-Junction Bipolar Transistors Exposed to Proton Irradiation

The degradation properties of Indium phosphide hetero-junction bipolar transistors (InP HBTs) under proton irradiation are studied and modelled using a compact model for pre-irradiation, post-irradiation, and post-annealing. The variation rates of the model parameters, such as the base–emitter saturation current (ISE) and ideality factor in the ideal region (NE) in the forward Gummel characteristics, the zero-biased capacitance (Cje) and the grading factor (Mjer) in the BE junction capacitance, and the transit time parameter in the base region (Tfb), are analysed to delve into the degradation mechanism induced by proton irradiation. The displacement damage, induced by proton irradiation in the space charge region of the base–emitter junction and in the quasi-neutral bulk base region, is found to be responsible for the decrease in current gain and cut-off frequency. After annealing, the variation rates of the parameters decrease significantly compared to post-irradiation. This suggests that the recombination of unstable defects leads to a slight recovery in the degradation characteristics of InP HBTs after a period of annealing.

The Study on Single-Event Effects and Hardening Analysis of Frequency Divider Circuits Based on InP HBT Process.

The single-event effects (SEEs) of frequency divider circuits and the radiation tolerance of the hardened circuit are studied in this paper. Based on the experimental results of SEEs in InP HBTs, a transient current model for sensitive transistors is established, taking into account the influence of factors such as laser energy, base-collector junction voltage, and radiation position. Moreover, the SEEs of the (2:1) static frequency divider circuit with the InP DHBT process are simulated under different laser energies by adding the transient current model at sensitive nodes. The effect of the time relationship between the pulsed laser and clock signal are discussed. Changes in differential output voltage and the degradation mechanism of unhardened circuits are analyzed, which are mainly attributed to the cross-coupling effect between the transistors in the differential pair. Furthermore, the inverted output is directly connected to the input, leading to a feedback loop and causing significant logic upsets. Finally, an effective hardened method is proposed to provide redundancy and mitigate the impacts of SEEs on the divider. The simulation results demonstrate a notable improvement in the radiation tolerance of the divider.

Incorporation of Ge on High K Dielectric Material for Different Fabrication Technologies (HBT, CMOS) and Their Impact on Electrical Characteristics of the Device

The paper is composed of distinct reviews on various fabrication technologies of the CMOS family and the characterization of MOS capacitors. The initial part of the article essentially presents a systemic review on an already conducted work on different fabrication technologies such as Si MOSFET, SiGe HBT, and InP HBT. Device and circuit-level performance for broadband and tuned millimetre-wave applications is discussed in detail relative to the underlying CMOS technologies. The comparison is made for various performance metrics for 180 nm, 130 nm, and 90 nm n-MOSFET devices for SiGe and InP HBTs. In the latter part of the study, a comprehensive review on a previously conducted research on electrical and physical characterization of metal-oxide-semiconductor (MOS) capacitors fabricated on a 2.5 μm epitaxial germanium layer grown on (100) silicon substrate is undertaken. The focus and crux of the study is the influence of germanium surface preparation on MOS electrical characteristics. It is observed that predielectric (HfO) deposition annealing in NH3 ambience results in the performance upgradation in critical and key parameters such as equivalent oxide thickness and the gate leakage current.

EM simulation assisted parameter extraction for transferred-substrate InP HBT modeling

AbstractIn this paper, an electromagnetic (EM) simulation assisted parameter extraction procedure is demonstrated for accurate modeling of down-scaled transferred-substrate InP HBTs. The external parasitic network associated with via transitions and device electrodes is carefully extracted from calibrated three-dimensional EM simulations up to 325 GHz. Following an on-wafer multi-line Through-Reflect-Line calibration procedure, the external parasitic network is de-embedded from the transistor measurements and the active device parameters are extracted in a reliable way. The small-signal model structure augmented with the distributed parasitic network provides accurate small-signal prediction up to 220 GHz.

W-Band InP HBT Power Amplifiers

This letter reports on two power amplifier (PA) monolithic microwave-integrated circuits operating at W-band. The PAs use 250 nm InP HBTs and thin-film microstrip topology formed with benzocyclobutene dielectric. First PA utilizes a two-emitter finger HBT unit cell with each finger having emitter area of $0.25 \times 6~\mu \text{m}^{2}$ . Second PA power combines two HBT unit cells. Both amplifiers are single stage and utilize conjugate matching at the input and optimum power load matching at the output. The first amplifier has demonstrated saturated output power of 12.4 dBm and power-added efficiency (PAE) of 41.7% at 93 GHz. This is the highest PAE number demonstrated at W-band. Second amplifier has demonstrated saturated output power of 15.6 dBm and PAE of 21.1% at 89 GHz.

Multifinger Indium Phosphide Double-Heterostructure Transistor Circuit Technology With Integrated Diamond Heat Sink Layer

The RF power output of scaled subterahertz and terahertz indium phosphide double-heterostructure bipolar transistors (InP DHBTs) is limited by the thermal device resistance, which increases with the geometrical frequency scaling of these devices. We present a diamond thin-film heat sink process aimed at the efficient removal of the heat generated in submicrometer InP HBTs. The thin-film diamond is integrated in a wafer bond process. Vertical connections are facilitated by plasma-processed contact holes through the diamond layer, metallized with electroplated gold. The process is suitable for monolithic circuit integration, amenable to the realization of high-power analog circuits in the millimeter-wave region and beyond. The thermal resistance of double-finger transistors with a 0.8- $\mu \text{m}$ emitter width could be reduced to 0.7 K/mW, while reaching the gain cutoff frequencies of $f_{T}=360$ GHz and $f_{\mathrm {max}}=350$ GHz. An integrated two-stage power amplifier with four-way power combining fabricated in this technology exhibited 20-dBm power output at 90 GHz with a bandwidth of 10 GHz.

A High-Linearity, 30 GS/s Track-and-Hold Amplifier and Time Interleaved Sample-and-Hold in an InP-on-CMOS Process

A high-speed, track-and-hold amplifier and interleaved CMOS sample-and-hold circuit are implemented in an InP-on-CMOS fabrication process. Conventional 50- $\Omega $ interchip interconnects between III-V and CMOS circuits are eliminated with heterogeneous integration of III-V on CMOS, yielding higher performance circuits at lower power consumption. The track-and-hold amplifier is based on a double-switching feedback architecture using 250 nm InP HBTs and achieves an IIP3 of 19 dBm at a sampling rate of 30 GS/s. To the author's knowledge, this is the first published result of a high-speed track-and-hold amplifier in an InP BiCMOS process and the first implementation of a feedback linearized track-and-hold at a sampling rate above 2 GS/s. Additionally, a novel HBT buffer with feedback is demonstrated to offer high linearity and low power for driving time-interleaved CMOS sample-and-hold circuits. A 90 nm time-interleaved CMOS sample-and-hold circuit is demonstrated to achieve better than $-$ 53 dBc ${\rm HD}_3$ at a sampling rate of 5 GS/s while consuming roughly 24 mW per channel.

0.8/2.2-GHz Programmable Active Bandpass Filters in InP/Si BiCMOS Technology

Programmable active bandpass filters (BPFs) have been designed in a chip-scale heterogeneous integration technology, which intimately integrates InP HBTs on a deep scaled CMOS technology. Therefore, the active BPF can leverage both high performance of InP HBT and high density and programmability of CMOS. Two BPF prototypes, consisting of a programmable gain amplifier (PGA), a fifth- or third-order BPF core, and a buffer, have been designed and fabricated. The BPF center frequency can be switched from 0.8 to 2.2 GHz with 150-MHz passband and delivers > 55-dB out-of-band (OOB) rejection for the fifth-order one. Four gain steps: 0, 6, 12, and 16 dB, are enabled by the front PGA to trade off noise and linearity performances. Due to the > 300-GHz f T of InP HBTs, the BPF cores can leverage active-RC architecture for high linearity owing to the close-loop implementation. The fifth-order BPF prototype occupies a 1.5 × 1.02 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area together with pads and draws 106/121 mA from a 3.3-V power supply for 0.8/2.2-GHz bands, respectively, which demonstrates OOB output third-order intercept points (OIP3s) of 22.69/21.25 dBm for 0.8/2.2-GHz bands at the high gain mode. The measurement results suggest the fifth-order BPF core achieves 36.69/35.25-dBm OOB OIP3s. In addition, the designed third-order programmable BPF has been successfully used as a technology yield vehicle to assist the BiCMOS technology development.

220-GHz High-Efficiency InP HBT Power Amplifiers

This paper reports on two power amplifier (PA) monolithic microwave integrated circuits (MMICs) operating at frequencies around 220 GHz. The PAs use 250-nm InP HBTs and thin-film microstrip technology formed with a benzocyclobutene dielectric. Both PAs utilize a two-emitter-finger HBT unit-cell with each finger having an emitter area of 0.25×6 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The single-stage amplifier MMIC has six two-emitter HBTs in parallel for a total emitter area of 18 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . This amplifier has ~ 5 dB of small-signal gain from 210 to 230 GHz. It has demonstrated saturated output power of 90 mW at 210 and power-added efficiency (PAE) of 10%. This is the highest PAE number demonstrated at these frequencies. The two-stage PA uses three single-stage PAs, one as a driver and two in a balanced configuration in the second stage. The total output emitter area is 18 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . This PA demonstrated saturated output > 100 mW and PAE ≥ 4% from 210 to 225 GHz.

A 0.8/2.4 GHz Tunable Active Band Pass Filter in InP/Si BiCMOS Technology

A tunable active band pass filter (BPF) has been designed in a chip-scale heterogeneous integration technology, which intimately integrates InP HBTs on a deep scaled CMOS technology. The BPF test chip consists of a programmable gain amplifier (PGA), a BPF core, and a buffer. The chip features a frequency tuning range from 0.8 to 2.4 GHz with 150 MHz pass band and four gain steps: 0, 6, 12, and 16 dB. The BPF core employs active-RC architecture for high linearity by leveraging the >300 GHz fT of InP HBTs and the programmability of CMOS. The test chip occupies 1.7×1.25 mm2 area including pads and draws 85/110 mA from a 3.5 V power supply for 0.8/2.4 GHz bands, respectively. In addition, it demonstrates out-of-band IIP3s of 21.97/16.87 dBm for 0.8/2.4 GHz bands at the high gain mode, which suggests the BPF core delivers 37.97/32.87 dBm out-of-band IIP3s.

(Invited) Heterogeneous Integration of InP HBTs on CMOS: Leveraging and Providing Value to Conventional Silicon Technologies

Historically, compound semiconductors have enjoyed the benefit of material properties that lend themselves to high performance electron devices, but the ability to fabricate complex, high transistor count ICs is limited by the relative immaturity of the material system and small commercial market. Silicon based devices have made significant advances in device performance, but have not yet matched compound semiconductor device performance. However, a large commercial market has allowed the silicon system to mature and produce billion transistor count ICs in high volume. It would be advantageous to combine the merits of both compound semiconductors and silicon based CMOS/BiCMOS to enable a new class of high performance ICs. This work will review HRL's efforts in wafer scale integration of an advanced 250nm, 350GHz fT/fMAX InP DHBT technology with RF-CMOS technologies whose device proximity; heterogeneous interconnect density; and additional technology features both leverage and provide additional value to conventional silicon technologies.

Heterogeneous Integration of InP HBTs on CMOS: Leveraging and Providing Value to Conventional Silicon Technologies

not Available.

High-Speed and High-Reliability InP-Based HBTs With a Novel Emitter

This paper describes InP HBTs with a novel emitter simply consisting of a degenerately doped n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -InGaAs layer and an undoped InP thin layer. An n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -InP layer is not necessary because the quasi-Femi level in the n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -InGaAs layer is high enough to exceed the conduction band discontinuity between the n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -InGaAs layer and the undoped InP layer. In the proposed structure, a thin ( ~ 10 nm) ledge structure can easily be fabricated by etching the n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -InGaAs layer. The fabricated HBTs with a 15-nm-thick ledge structure provide a high collector current density of over 6 mA/¿m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . There is almost no degradation of current gain, although the emitter width is reduced to as small as 0.5 ¿m. The HBTs also exhibit an <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ft</i> of 324 GHz at a collector current density of 5.5 mA/¿m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , which is comparable with that of HBTs with a conventional emitter consisting of an n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -InGaAs layer, an n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -InP layer, and an n-InP layer. From the results of accelerated life tests, the activation energy of the degradation in HBTs is estimated to be around 1.8 eV, and the extrapolated mean time to failure is estimated to be over 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> h at a junction temperature of 125°C.

A 90-Gb/s Modulator Driver IC Based on Functional Distributed Circuits for Optical Transmission Systems

A monolithic modulator driver IC based on InP HBTs with a new circuit topology — called a functional distributed circuit (FDC) — for over 80-Gb/s optical transmission systems has been developed. The FDC topology includes a wide-band amplifier designed using a distributed circuit, a digital function designed using a lumped circuit, and broadband impedance matching between the lumped circuit and distributed circuit to enable both wider bandwidth and digital functions. The driver IC integrated with a 2: 1 multiplexing function produces 2.6-Vp-p (differential output: 5.2Vp-p) and 2.4-Vp-p (differential output: 4.8Vp-p) output-voltage swings with less than 450-fs and 530-fs rms jitter at 80Gb/s and 90Gb/s, respectively. To the best of our knowledge, this is equivalent to the highest data rate operation yet reported for monolithic modulator drivers. When it was mounted in a module, the driver IC successfully achieved electro-optical modulation using a dual-drive LiNbO3 Mach-Zehnder modulator up to 90Gb/s. These results indicate that the FDC has the potential to realize high-speed and functional ICs for over-80-Gb/s transmission systems.

Study of a PMD Tolerance Extension by InP HBT Analog EDC IC without Adaptive Control in 43G DQPSK Transmission

We experimentally studied the polarization mode dispersion (PMD) tolerance of an feed-forward equalizer (FFE) electronic dispersion compensation (EDC) IC in the absence of adaptive control, in 43-Gbit/s RZ-DQPSK transmission. Using a 3-tap FFE IC composed of InP HBTs, differential group delay (DGD) tolerance at a 2-dB Q penalty is shown to be extended from 25ps to up to 29ps. When a polarization scrambler is used, the tolerance is further extended to 31ps. This value is close to the tolerance obtained with adaptive control, without a polarization scrambler.

Introduction to the Special Section on the IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS 2008)

The five papers selected for this Special Section, chosen in part based on symposium attendee survey feedback, highlight some of the most significant achievements reported at the meeting. The first paper describes a WCDMA base-station power amplifier utilizing GaAs high-voltage HBTs and a wideband envelope tracking system to achieve high power, high linearity performance at higher efficiency than competing technologies. The next two papers demonstrate the remarkable versatility and performance of state-of-the-art GaN technology. The fourth paper presents a SiGe HBT-based 80 GHz voltage-controlled oscillator (VCO) with a very wide tuning rage for applications such as 77 GHz automotive radar. And the final paper describes >100 GHz gain-bandwidth amplifier enabled using a novel wafer bonding approach to heteregeneous integration of InP HBTs and conventional 130 nm CMOS.

Monolithic III-V/Si Integration

We summarize our work on creating substrate platforms, processes, and devices for the monolithic integration of silicon CMOS circuits with III-V optical and electronic devices. Visible LEDs and InP HBTs have been integrated on silicon materials platforms that lend themselves to process integration within silicon fabrication facilities. We also summarize research on tensile Ge, which could be a high mobility material for III-V MOS, and research on an in-situ MOCVD Al2O3/GaAs process for III-V MOS.

Emitter-metal-related degradation in InP-based HBTs operating at high current density and its suppression by refractory metal

We investigated the reliability of InP-based HBTs with a ledge structure, focusing on emitter-metal-diffusion-induced degradation. Bias-temperature accelerated tests under high temperatures and high current densities of up to 5 mA/μm 2 were conducted for HBTs with conventional emitter electrodes, whose metal configuration was Ti/Pt/Au, and for HBTs with refractory metal emitters of Ti/Mo–Ti/Pt/Au, Ti/W–Ti/Pt/Au, or W–Ti/Pt/Au. The emitter contact layer was analyzed by transmission electron microscopy, energy dispersive X-ray spectroscopy, and transmission electron diffraction. Severe damage and disruption of uniformity of the atomic composition were observed due to diffusion of Ti and Au in HBTs with conventional emitter, whereas suppression of those degradations was observed in HBTs with refractory emitter. Refractory metals were found to be advantageous for blocking upper metal diffusion. Interstitials of host species generated due to metal diffusion must cause a shift of atomic composition. The time-wise change in the emitter resistance was estimated to compare the speed of the contact layer degradation between different emitter electrode metals. The critical time, which we determined as an emitter resistance increases of 3% from the initial value, increased by one order for HBTs with refractory metal than for HBTs with conventional metal at the same junction temperature, despite the same activation energy of 2.0 and 1.65 eV for J c of 2 and 5 mA/μm 2, respectively, for all types of emitter electrode. The advantages of refractory metal for improving the reliability of InP HBTs were confirmed, especially for operation at high current densities.

Reliability of InP-based HBTs at High Current Density

AbstractInP-based HBTs for ultrahigh speed optical communications systems operation at over 40 GHz require a long-term stability under high current injection conditions, such as current densities of 2 or 5 mA/μm2. We achieved high reliability by suppressing surface recombination and emitter-metal-related crystalline degradation.Changes in the electric properties of devices due to temperature and bias stress were evaluated. The reduction in DC current gain due to surface recombination had the activation energy of 1.7 eV without current density dependence, and the lifetime of HBTs for this degradation mode is predicted to be over 1×108 hours at 125°C. The emitter metal diffusion and disruption of uniformity of the atomic composition were observed by transmission electron microscopy and energy dispersive X-ray spectroscopy in HBTs with the conventional Ti/Pt/Au emitter, whereas suppression of those degradations was observed in HBTs with refractory metal of Mo and W. The emitter resistance was estimated to evaluate the contact layer degradation. The critical time was one order larger for HBTs with refractory metal than for HBTs with conventional metal. The activation energies for resistance increases were 2.0 and 1.65 eV for the current density of 2 and 5 mA/μm2, respectively, for all types of emitter electrodes.The effectiveness of the refractory metal electrode for improving device reliability was confirmed, especially in high-current-density operation, which is essential for applying InP HBTs in high-speed ICs.