InP Double Heterojunction Bipolar Transistor Research Articles

High-performance uniform stepper-based InP double-heterojunction bipolar transistor (DHBT) on a 3-inch InP substrate

In this paper, InP Double-Heterojunction Bipolar Transistors (DHBTs) on a 3-inch InP substrate is demonstrated through stepper-based photolithography. The performance of the fabricated InP DHBTs such as DC characteristics, high-frequency characteristics, and uniformity of the 3-inch wafer is investigated to verify the stepper-based fabrication process. To improve the high-frequency characteristics, the self-aligned base-emitter contact is realized by using the high height-to-width ratio and vertical sidewall emitter profile of the Au electroplating process. The fabricated DHBTs with WE = 0.6 μm and LE = 15 μm exhibits current gain (β) = 50 at VCE = 1.0 V and an open-base common-emitter breakdown voltage (BVCEO) of 5.7 V at JC = 0.01 mA/µm2 and 7.5 V at JC = 0.1 mA/µm2, respectively. Moreover, the fabricated DHBTs with WE = 0.6 μm and LE = 15 μm show excellent fT of 244 GHz and fmax of 221 GHz at JC = 4.4 mA/μm2 and VCE = 1.6 V. In order to evaluate the uniformity of the fabricated DHBTs, we measure current gain (β) and high-frequency characteristics with WE = 0.6 μm and LE = 15 μm and the average values and standard deviation of the β, fT, and fmax are β = 49.3 ± 1.9, fT = 241.4 ± 3.8 GHz, and fmax = 221.5 ± 4.0 GHz, respectively. Thanks to the optimized stepper-based fabrication process, the fabricated InP DHBTs exhibit well-balanced high-frequency characteristics and excellent uniformity.

InP DHBT Analytical Modeling: Toward THz Transistors

InP double heterojunction bipolar transistors (InP DHBT) are one of the key technologies considered for terahertz applications. Improvement of their frequency performance is challenging and strongly dependent on various parameters (manufacturing process, geometry, epitaxial structure). In this article, a novel method is developed to take into account these parameters and predict the frequency performance of the technology. This approach consists of rebuilding the S-parameter matrix of the small-signal model. Elements of the small signal model are identified, and their assessment is described in detail. Once calibrated with the present state-of-the-art device features, the model shows a good agreement with the measurements. Based on this result, analysis of the emitter and base technological features are performed along with optimizations of the vertical structure. Finally, the necessary optimizations for developing a terahertz transistor are detailed. This works provides guidelines for technological improvement and opens the way for designing transistors operating at frequencies above a terahertz.

RF characterization of InP double heterojunction bipolar transistors on a flexible substrate under bending conditions

This letter presents the fabrication of InP double heterojunction bipolar transistors (DHBTs) on a 3-inch flexible substrate with various thickness values of the benzocyclobutene (BCB) adhesive bonding layer, the corresponding thermal resistance of the InP DHBT on flexible substrate is also measured and calculated. InP DHBT on a flexible substrate with 100 nm BCB obtains cut-off frequency f T = 358 GHz and maximum oscillation frequency f MAX = 530 GHz. Moreover, the frequency performance of the InP DHBT on flexible substrates at different bending radii are compared. It is shown that the bending strain has little effect on the frequency characteristics (less than 8.5%), and these bending tests prove that InP DHBT has feasible flexibility.

An electromagnetic simulation assisted small signal modeling method for InP double-heterojunction bipolar transistors

We present a convenient and practical electromagnetic (EM) assisted small-signal model extraction method for InP double-heterojunction bipolar transistors (DHBTs). Parasitic parameters of pad and electrode fingers are extracted by means of 3D EM simulation. The simulations with a new excitation scheme are closer to the actual on-wafer measurement conditions. Appropriate simulation settings are calibrated by comparing measurement and simulation of OPEN and SHORT structures. A simpler π-type topology is proposed for the intrinsic model, in which the base-collector resistance Rμ , output resistance R ce are deleted, and a capacitance C ce is introduced to characterize the capacitive parasitic caused by the collector finger and emitter ground bar. The intrinsic parameters are all extracted by exact equations that are derived from rigorous mathematics. The method is characterized by its ease of implementation and the explicit physical meaning of extraction procedure. Experimental validations are performed at four biases for three InGaAs/InP HBT devices with 0.8 × 7 μm, 0.8 × 10 μm and 0.8 × 15 μm emitter, and quite good fitting results are obtained in the range of 0.1–50 GHz.

A 32.2 GHz Full Adder Designed with TLE Method in a InP DHBT Technology

Ultra-high-speed full adder is the bottleneck in a tens of GHz Direct digital synthesizer (DDS). In this paper, a 32.2 GHz, 1bit full adder in a 0.7 μm InP double hetero-junction bipolar transistor (DHBT) technology is presented. In such a high-speed circuit, signal integrity is a crucial issue. Therefore, a transmission line equivalent (TLE) method is proposed. With the TLE method, the design of the full adder could be simplified with good accuracy. The synchronous latch is combined with adding operation to improve the calculation speed. A single-level parallel-gated circuit is designed using majority decision algorithm to reduce power consumption. Measurement results show that the maximum clock frequency of the full adder is 32.2-GHz, and the overall power consumption is 350 mW. The full adder is successfully adopted in a 17 GHz, 8 bit DDS which can synthesize sin-wave outputs from 66.41 MHz to 8.5 GHz in 66.41 MHz steps with an average Spurious-Free Dynamic Range (SFDR) of -18.1 dBc.

A 56–161 GHz Common-Emitter Amplifier with 16.5 dB Gain Based on InP DHBT Process

This paper presents a broadband amplifier MMIC based on 0.5 µm InP double-heterojunction bipolar transistor (DHBT) technology. The proposed common-emitter amplifier contains five stages, and bias circuits are used in the matching network to obtain stable high gain in a broadband range. The measurement results demonstrate a peak gain of 19.5 dB at 146 GHz and a 3 dB bandwidth of 56–161 GHz (relative bandwidth of 96.8%). The saturation output power achieves 5.9 and 6.5 dBm at 94 and 140 GHz, respectively. The 1 dB compression output power is −4.7 dBm with an input power of −23 dBm at 94 GHz. The proposed amplifier has a compact chip size of 1.2 × 0.7 mm2, including DC and RF pads.

A Beyond-1-Tb/s Coherent Optical Transmitter Front-End Based on 110-GHz-Bandwidth 2:1 Analog Multiplexer in 250-nm InP DHBT

This article presents an optical transmitter front-end based on 2:1 analog multiplexer (AMUX) for beyond-1-Tb/s/carrier coherent optical communications systems. An AMUX is monolithically integrated with an optical modulator driver to realize an AMUX-Driver IC that can directly drive an optical modulator. The AMUX-Driver IC fabricated by using our in-house 250-nm InP double heterojunction bipolar transistors (DHBTs), which have a peak cutoff frequency ( $f_{\mathrm {T}}$ ) and maximum oscillation frequency ( $f_{\mathrm {max}}$ ) of 460 and 480 GHz, respectively, achieves a record bandwidth of 110 GHz and a 1.5- $\text{V}_{\mathrm {ppd}}$ linear differential output range with a <3% total harmonic distortion (THD). A coherent optical transmitter front-end module compactly integrating two AMUX-Driver ICs and an InP-based optical in-phase quadrature (IQ) modulator achieves an electro-optic (EO) bandwidth higher than 80 GHz at the 6-dB point. Beyond-1-Tb/s/carrier optical modulation based on 168-GBaud polarization-division-multiplexed (PDM) 16-ary quadrature-amplitude-modulation (16QAM) was successfully demonstrated by using this integrated module.

A 300-GHz High-Power High-Efficiency Voltage-Controlled Oscillator With Low Power Variation

This letter presents a 300-GHz voltage-controlled oscillator (VCO) with high output power and efficiency. The VCO core employs a differential Colpitts topology with inductive degeneration to facilitate a fundamental oscillation at 300 GHz. A common-base output buffer regulates the output power to minimize the power variation during the frequency tuning. The 300-GHz VCO is fabricated in a 130-nm InP double heterojunction bipolar transistor (DHBT) technology. The VCO exhibits a measured frequency tuning range of 9.9 GHz (294.9–304.8 GHz). The peak output power is measured to be 4.7 dBm at 297 GHz. The dc power consumption is 75.6 mW, leading to a high dc-to-RF conversion efficiency of 3.9%. The VCO output power is maintained nearly constant with only a 0.3-dB variation over the entire frequency tuning range. The phase noise is −86.6 dBc/Hz at 10-MHz offset frequency.

InGaP/GaAsSb/InGaAsSb/InP Double Heterojunction Bipolar Transistors With Record f t of 813 GHz

We fabricated InGaP/GaAsSb/InGaAsSb/InP double heterojunction bipolar transistors (DHBTs) with an aggressive lateral and vertical scaling technology to improve the current gain cutoff frequency ( ${f}_{\text {t}}$ ) further. A 13-nm-thick GaAsSb/InGaAsSb base and a 40-nm-thick InP collector are used to reduce electron transit time. In addition, the width of the base electrode on each side of the emitter is reduced to about 0.05 $\mu \text{m}$ to suppress increases in parasitic collector capacitance. A fabricated DHBT with the emitter size of 0.24 $\mu \text{m}\,\,\times7.8\,\,\mu \text{m}$ exhibits maximum differential current gain of ~95 and collector-emitter breakdown voltage of 2.6 V. At a collector current density of 18 mA/ $\mu \text{m}^{{2}}$ , the DHBT exhibits ${f}_{\text {t}}$ of 813 GHz, which is the highest among all types of transistors measured at a room temperature.

300‐GHz integrated heterodyne receiver with carrier lock‐in Costas loop

A carrier signal lock-in experiment using a 300-GHz integrated heterodyne circuit is presented. The circuit contains a single voltage-controlled oscillator with a single set of quadrature mixers that are fabricated using 250-nm InP double hetero-junction bipolar transistor technology. An external feedback loop containing packaged baseband components such as amplifiers, a phase discriminator, and a filter is connected to the integrated circuit to form a complete receiver system. For a −25 dBm of input RF signal with 3.5-GHz single-tone carrier-suppressed modulation, the receiver system responds with successful lock-in range of 110 MHz centred around 311 GHz.

Performance Analysis of a Low-Noise, Highly Linear Distributed Amplifier in 500-nm InP/InGaAs DHBT Technology

This article is an extension of the previous report on an ultrawideband distributed amplifier (DA) in the InP double heterojunction bipolar transistor (DHBT) technology. With the choice of a tricode unit cell, the Miller capacitance is reduced and a larger bandwidth (BW) is obtained. Measured S-parameters show a 3-dB BW of near dc to >170 GHz with a gain of 12 dB. In addition, the circuit operates in low dc bias conditions, thus yielding a low measured noise figure (NF) of 8 dB over the frequency range of 5–50 GHz and 12 dB at 135 GHz. Within the 5–50-GHz frequency range, the NF is only 0.5 dB higher than the NF of a similar DA with cascode unit cell. When the circuit is measured for large-signal condition, it reaches a 1-dB output compression point, $P_{\mathrm {1\,dB}}$ , of 8.4 dBm at 150 GHz, a saturated output power of approximately 10 dBm, and an associated maximum power-added efficiency (PAE) of 6%. This is the best linearity as well as the highest saturated output power and PAE reported at this frequency for DAs. When measured at 20 GHz, the circuit shows a $P_{\mathrm {1\,dB}}$ , of 9 dBm and output referred third-order intercept point of 22 dBm, a saturated output power of 11 dBm, and an associated maximum PAE of 6%, thereby proving its uniform large-signal character within the full band. In short, this circuit brings in the unique combination of low NF, highly linear characteristics, and high PAE simultaneously together over large BW. Furthermore, the circuit consumes 180 mW of dc power only.

A Multiscale TCAD Approach for the Simulation of InP DHBTs and the Extraction of Their Transit Times

A multiscale technology computer-aided design (TCAD) simulation methodology is presented to calculate the intrinsic transit time of InP double heterojunction bipolar transistors (DHBTs). A 2-D hyd-rodynamic (HD) simulator is employed to produce the dc characteristics and electrostatic potentials of the selected devices. Utilizing the cuts of the obtained potential profiles as inputs, a 1-D full-band, atomistic quantum transport (QT) solver is then deployed to determine the ballistic electronic transport properties of these components. The transit times of DHBTs based on InGaAs/InP and GaAsSb/InP technologies are finally investigated with the proposed approach. Good qualitative agreements are observed with the experimental measurements. The observed underestimations of the experimental transit times are justified with the physics-based compact model HiCuM, thus providing a basis for structure and performance optimizations toward real terahertz transistors.

Efficient active multiplier‐based signal source for &gt;300 GHz system applications

This Letter presents a 300 GHz signal source, realised using an 800 nm transferred-substrate InP double heterojunction bipolar transistor process. The source is based on an active frequency tripler. It delivers −1.6 dBm peak output power at 306 GHz. The DC consumption is only 36 mW, which corresponds to 2% conversion efficiency. The measured tripler achieves more than 30 GHz bandwidth and exhibits very low unwanted harmonics. The chip area of the source is only 0.94 × 0.84 mm2.

Design and modeling of an ultra-wideband low-noise distributed amplifier in InP DHBT technology

AbstractThis paper reports on an ultra-wideband low-noise distributed amplifier (LNDA) in a transferred-substrate InP double heterojunction bipolar transistor (DHBT) technology which exhibits a uniform low-noise characteristic over a large frequency range. To obtain very high bandwidth, a distributed architecture has been chosen with cascode unit gain cells. Each unit cell consists of two cascode-connected transistors with 500 nm emitter length and ft/fmax of ~360/492 GHz, respectively. Due to optimum line-impedance matching, low common-base transistor capacitance, and low collector-current operation, the circuit exhibits a low-noise figure (NF) over a broad frequency range. A 3-dB bandwidth from 40 to 185 GHz is measured, with an NF of 8 dB within the frequency range between 75 and 105 GHz. Moreover, this circuit demonstrates the widest 3-dB bandwidth operation among all reported single-stage amplifiers with a cascode configuration. Additionally, this work has proposed that the noise sources of the InP DHBTs are largely uncorrelated. As a result, a reliable prediction can be done for the NF of ultra-wideband circuits beyond the frequency range of the measurement equipment.

A 220-GHz InP DHBT Power Amplifier With Integrated Planar Spatial Power Combiner

In this letter, we present a research on the application possibility of the integrated planar spatial (IPS) combiner in terahertz monolithic integrated circuits (TMICs). The IPS combiner has several attractive characters, such as low loss and good port-to-port isolation. Measured insertion loss of the back-to-back four-way IPS combiner prototype is less than 1.65 dB from 220 to 260 GHz. Then, the IPS power combiner is applied to a four-way six-stage common-emitter InP double heterojunction bipolar transistor amplifier based on a 0.5- $\mu \text{m}$ process. With the help of the IPS combiner and the compact circuit design, this letter greatly improves the output power and output power density compared with other TMICs of the same InP HBT technology. The output power density per unit emitter length (output stage) is 0.51 mW/ $\mu $ m, which is at the same level of amplifiers based on the 0.25- $\mu \text{m}$ InP HBT technology.

InGaAs/InP DHBT small‐signal model up to 325 GHz with two intrinsic base resistances

AbstractIn this paper, a novel small‐signal equivalent‐circuit model of terahertz InGaAs/InP double‐heterojunction bipolar transistor (DHBT) is presented. Two intrinsic base resistances are introduced to represent the nonuniform extrinsic impedance of base‐emitter and base‐collector junctions separately. This treatment makes the high‐frequency model more close to the triple‐mesa InP DHBT structure. Systematical parasitic parameter extraction method and intrinsic element initialization of a 0.5 μm * 5μm InGaAs/InP DHBT are presented. As a high‐frequency device model, inter‐electrode parasitic capacitances are calculated by three‐dimensional electromagnetic simulation. The proposed model results in a good agreement with measured multibiased S‐parameters up to 325 GHz.

A Highly Efficient Ultrawideband Traveling-Wave Amplifier in InP DHBT Technology

This letter presents a 1 to >110-GHz ultrawideband traveling-wave amplifier (TWA) based on 500-nm transferred-substrate InP double-heterojunction bipolar transistor technology. The HBT cells are realized with inductive peaking at the output and match the phase delay between individual stages. The collector bias is slightly below the value for the maximum current gain. This allows a frequency-invariant high-output power characteristic with a flat group delay. The amplifier exhibits a gain of 13 dB with a measured bandwidth of 1–110 GHz and a uniform 10-dBm 1-dB compression output power with an associated maximum PAE of 8% at 110 GHz. To the best of our knowledge, this is the highest PAE and the maximum flat output power reported for such a TWA covering frequencies up to 170 GHz. The amplifier consumes only 129 mW, which is among the lowest dc power dissipations reported for the given gain–bandwidth product. Moreover, the group delay is flat across the band, which makes the TWA very useful in high-speed optical communication systems.

Optimization of InP DHBT stacked-transistors for millimeter-wave power amplifiers

AbstractIn this paper, we report the analysis, design, and implementation of stacked transistors for power amplifiers realized on InP Double Heterojunction Bipolar Transistors (DHBTs) technology. A theoretical analysis based on the interstage matching between all the single transistors has been developed starting from the small-signal equivalent circuit. The analysis has been extended by including large-signal effects and layout-related limitations. An evaluation of the maximum number of transistors for positive incremental power and gain is also carried out. To validate the analysis, E-band three- and four-stacked InP DHBT matched power cells have been realized for the first time as monolithic microwave integrated circuits (MMICs). For the three-stacked transistor, a small-signal gain of 8.3 dB, a saturated output power of 15 dBm, and a peak power added efficiency (PAE) of 5.2% have been obtained at 81 GHz. At the same frequency, the four-stacked transistor achieves a small-signal gain of 11.5 dB, a saturated output power of 14.9 dBm and a peak PAE of 3.8%. A four-way combined three-stacked MMIC power amplifier has been implemented as well. It exhibits a linear gain of 8.1 dB, a saturated output power higher than 18 dBm, and a PAE higher than 3% at 84 GHz.

An investigation of the DC and RF performance of InP DHBTs transferred to RF CMOS wafer substrate * * Project supported by the National Natural Science Foundation of China (No. 61331006) and the Natural Science Foundation of Zhejiang Province (No. Y14F010017).

This paper investigated the DC and RF performance of the InP double heterojunction bipolar transistors (DHBTs) transferred to RF CMOS wafer substrate. The measurement results show that the maximum values of the DC current gain of a substrate transferred device had one emitter finger, of 0.8 μm in width and 5 μm in length, are changed unobviously, while the cut-off frequency and the maximum oscillation frequency are decreased from 220 to 171 GHz and from 204 to 154 GHz, respectively. In order to have a detailed insight on the degradation of the RF performance, small-signal models for the InP DHBT before and after substrate transferred are presented and comparably extracted. The extracted results show that the degradation of the RF performance of the device transferred to RF CMOS wafer substrate are mainly caused by the additional introduced substrate parasitics and the increase of the capacitive parasitics induced by the substrate transfer process itself.

Design and Analysis of a Wideband Gilbert Cell VGA in 0.25- $\mu {\rm m}$ InP DHBT Technology With DC-40-GHz Frequency Response

A differential variable gain amplifier (VGA) for wideband baseband signals has been designed, analyzed, and implemented in a 0.25- $\rm \mu m$ InP double heterojunction bipolar transistor technology with $f_{T}/f_{\mathrm{ max}}$ of 370/650 GHz. The 3-dB frequency bandwidth is measured to be 40 GHz with a maximum gain of 31 dB, resulting in a gain bandwidth product (GBP) of 1.4 THz, four times higher than previously reported GBP from a Gilbert cell-based VGAs. Furthermore, it measures a gain control range of 44 dB, a noise figure of 6.2 dB, an output third-order intercept point of 17 dBm, and a total power consumption of 350 mW from a single −7-V supply. With pseudorandom binary sequence test pattern signals, a clear open eye at 44 Gb/s was observed. The complete circuit, including on-chip integrated bias network and pads, measures 0.77 $\rm mm^{2}$ . We analyze the VGA for the 3-dB bandwidth and GBP by the use of zero-value time constants method to analytically identify the maximum GBP with respect to the design parameters and current bias.