InGaAs HEMT Research Articles

Silicon-based integrated passive device stack for III-V/Si monolithic 3D circuits operating on RF band

In this study, we demonstrated a silicon (Si)-based integrated passive device (IPD) stack to support III-V/Si monolithic 3D (M3D) ICs operating on the radio frequency (RF) band. The IPD stack was fabricated based on an 8-inch CMOS process line and integrated via M3D with an InGaAs HEMT layer. A process condition for a trap rich layer and a buried oxide layer in the IPD was established to simultaneously minimizing both the RF loss and wafer bowing. Through the process condition, the RF loss of the coplanar waveguides was −0.631 dB/mm at 30 GHz, lower than that of the CMOS foundry, and the wafer bowing of the stack was as low as −5.5 μm. The maximum quality factor of the inductors showed good values when compared to those of other CMOS foundry process-based inductors operating on the RF bands reported thus far. To obtain a compressive profile for the IPD stack, which is one of the most important requirements in advancing to wafer-to-wafer-level 3D bonding with the III-V active layer, a process method for the final IMD layer of the IPD was developed, resulting in a change from a tensile profile to a compressive profile for the IPD (corresponding wafer bowing value from −12.6 to + 10.7 μm).

Thermal Studies of 3-D Stacked InGaAs HEMTs and Mitigation Strategy of Self-Heating Effect Using Buried Metal Insertion

Thermal Studies of 3-D Stacked InGaAs HEMTs and Mitigation Strategy of Self-Heating Effect Using Buried Metal Insertion

Influence of Channel Structure on the Subthreshold Swing of InGaAs HEMTs at Cryogenic Temperatures Down to 4 K

Influence of Channel Structure on the Subthreshold Swing of InGaAs HEMTs at Cryogenic Temperatures Down to 4 K

A New Analytical Large-Signal Model for Quasi-Ballistic Transport in InGaAs HEMTs Accommodating Dislocation Scattering

A surface-potential-based analytical large-signal model, which is applicable to both ballistic and quasi-ballistic transport in InGaAs high electron mobility transistors, is developed. Based on the one-flux method and a new transmission coefficient, a new two-dimensional electron gas charge density is derived, while the dislocation scattering is novelly taken into account. Then, a unified expression for Ef valid in all the regions of gate voltages is determined, which is utilized to directly calculate the surface potential. The flux is used to derive the drain current model incorporating important physical effects. Moreover, the gate-source capacitance Cgs and gate-drain capacitance Cgd are obtained analytically. The model is extensively validated with the numerical simulations and measured data of the InGaAs HEMT device with the gate length of 100 nm. The model is in excellent agreement with the measurements under I-V, C-V, small-signal conditions, and large-signal conditions.

Comparison of GaN and InGaAs high electron mobility transistors as zero-bias microwave detectors

We report on the measurements of the two main figures of merit for microwave detection, namely, responsivity and noise equivalent power (NEP), in HEMTs based on two of the most broadly used material systems AlGaN/GaN and AlInAs/InGaAs. A comparison between their performances as RF detectors in a wide temperature range is provided by means of experiments made under probes with direct connection to the drain contact. InGaAs HEMTs exhibit much better responsivity and NEP, which are further improved when lowering the working temperature. Moreover, we analyze the possibility of optimizing the current-mode detection of the transistors by improving the impedance matching conditions through an adequate choice of the device width W.

Efficient TCAD Thermal Analysis of Semiconductor Devices

We present an efficient numerical technique for the temperature-dependent TCAD analysis of semiconductor devices. The approach is based on the linearization of the physical model around a nominal temperature operating condition, and exploits the Green’s functions (GFs) of the physical model to estimate the device characteristics at a different temperature. Self-heating can also be accounted for through coupling an external thermal circuit, with no numerical overhead. In the static (dc) case, the thermal analysis can be readily implemented in TCAD tools, using GFs customarily used for the electron device noise and variability analyses. The proposed technique is also extended to the dynamic case, to model the temperature dependence of electron devices operating in large signal conditions. We provide an extensive validation of the GF-based thermal analysis, including simulations of a 22-nm FinFET and of an InGaAs HEMT with 250 nm gate length. In the dynamic case, we demonstrate the efficient thermal analysis of a medium power amplifier in a FinFET technology.

(Invited) Monolithic Integration of Si-CMOS and III-V-on-Si through Direct Wafer Bonding Process

Integration of Si-CMOS and III-V compound semiconductors (with device structures of either InGaAs HEMT, AlGaInP LED, GaN HEMT or InGaN LED) on a common Si substrate is demonstrated. The Si-CMOS layer is temporarily bonded on a Si handle wafer. Another III-V/Si substrate is then bonded to the Si-CMOS containing handle wafer. Finally, the handle wafer is released to realize the Si-CMOS on III-V/Si substrate. For GaN HEMT or LED on Si substrate, additional wafer bonding step is required to replace the fragile Si (111) substrate after high temperature GaN growth with a new Si (001) wafer to improve the robustness of the GaN/Si wafers. Through this substrate replacement step, the bonded wafer pair can survive the subsequent processing steps. The monolithic integration of Si-CMOS + III-V devices on a common Si platform enables new generation of systems with more functionality, better energy efficiency, and smaller form factor.

(Invited) Monolithic Integration of Si-CMOS and III-V-on-Si through Direct Wafer Bonding Process

Integration of Si-CMOS and III-V compound semiconductors (with device structures of either InGaAs HEMT, InGaP LED, GaAs HBT, GaN HEMT or InGaN LED) on a common Si substrate is demonstrated. The Si-CMOS layer is temporarily bonded on a Si handle wafer. Another III-V/Si substrate is then bonded to the Si-CMOS containing handle wafer. Finally, the handle wafer is released to realize the Si-CMOS on III-V/Si substrate. For GaN LED or HEMT on Si substrate, additional wafer bonding step is required to replace the fragile Si (111) substrate after high temperature GaN growth with a new Si (001) wafer to improve the robustness of the GaN/Si wafers. Through this substrate replacement step, the bonded wafer pair can survive the subsequent processing steps. The monolithic integration of Si-CMOS + III-V devices on a common Si platform enables new generation of systems with more functionality, better energy efficiency, and smaller form factor.

Monolithic Integration of Si-CMOS and III-V-on-Si Through Direct Wafer Bonding Process

Integration of silicon-complementary metal oxide-semiconductor (Si-CMOS) and III-V compound semiconductors (with device structures of either InGaAs HEMT, AlGaInP LED, GaN HEMT, or InGaN LED) on a common Si substrate is demonstrated. The Si-CMOS layer is temporarily bonded on a Si handle wafer. Another III-V/Si substrate is then bonded to the Si-CMOS containing handle wafer. Finally, the handle wafer is released to realize the Si-CMOS on III-V/Si substrate. For GaN HEMT or LED on Si substrate, additional wafer bonding step is required to replace the fragile Si (111) substrate after high temperature GaN growth with a new Si (001) wafer to improve the robustness of the GaN/Si wafers. Through this substrate replacement step, the bonded wafer pair can survive the subsequent processing steps. The monolithic integration of Si-CMOS + III-V devices on a common Si platform enables new generation of systems with more functionality, better energy efficiency, and smaller form factor.

(Invited) SiGe and III-V Materials and Devices: New HEMT and LED Elements in 0.18-Micron CMOS Process and Design

The incorporation of new materials into CMOS scaling has become a necessity. Our previous work in SiGe and III-V integration shows promise in allowing further materials integration for increased transistor density. However, a principal concern is that investment returns by further increasing transistor density will likely be negative for all but possibly one or two corporations, and may be negative for all. Moore’s Law metrics for the benefits of incorporating III-V and other materials monolithically into silicon CMOS are not sufficient to determine innovative value for CMOS+X combinations. Such an environment that cannot use traditional metrics is a challenge for all organizations participating in the previous paradigm. Despite these challenging times, we list the likely characteristics of a new innovation path, and describe our efforts to follow it through research into ‘white space’ integrated circuits employing new materials and devices. Initially, we are designing novel integrated circuits, materials and processes incorporating GaN HEMTs, GaN and AlInGaP LEDs, and InGaAs HEMTs monolithically into existing silicon CMOS foundry processes. Both heteroepitaxy and wafer bonding are used in the process flow, and SiGe or Ge buffer layers are used in many processes. A modular process flow is incorporated so that the new devices can be modeled and incorporated into the design kit for a foundry process, allowing us to leverage much of the existing silicon design and manufacturing infrastructure. Our initial focus is on the demonstration of wafer-level integration of III-V devices with foundry 0.18 -micron CMOS devices on 200 mm wafers, and we report on the progress made in materials, device and circuit design towards this goal.

High power efficiency distributed oscillator based on composite-right-/left-handed unit cells

A microwave oscillator topology based on CRLH (Composite Right-/Left-Handed) unit cells is analyzed theoretically and experimentally tested. The oscillator consists of a CRLH based distributed amplifier and a positive feedback realized by a simple transmission line. The oscillator has two output ports, where the power levels are practically the same. For this topology, we have found the oscillation condition and we demonstrate that each transistor gives the same contribution to the power delivered at the two output ports, in this way, the output power is maximized. The oscillator has been designed for a frequency of oscillation of 2.8 GHz and fabricated in hybrid technology, by using InGaAs HEMTs and microstrip lines. The measured powers at the two output ports are equal to 12.6 dBm and 10.4 dBm, the small difference between these values being given by the insertion loss of the gate line. The experimental frequency of oscillation is 2.77 GHz, with a difference of less than 1% in comparison with the expected value. Due to the frequency selectivity of the CRLH unit cells, numerical simulations predict low phase noise for this configuration of oscillator.

An Improved Virtual-Source-Based Transport Model for Quasi-Ballistic Transistors—Part II: Experimental Verification

In the first part of this two-part paper, a revised MIT virtual-source (MVS)-based transport model, called MVS-2, is presented. The MVS-2 model captures the essential physics of quasi-ballistic nanotransistors by accounting for the effects of: 1) degeneracy on the thermal velocity and the mean free path of the carriers in the channel; 2) nonequilibrium transport conditions on the gate–channel capacitance; and 3) the conduction band nonparabolicity on the effective mass of the carriers. The formulation of the extrinsic device regions as nonlinear current-dependent resistances allows MVS-2 to describe the degradation in the device transconductance under high drain currents as measured experimentally in InGaAs quantum well HEMT devices. In this paper, we test the accuracy of the MVS-2 model by comparing the model results with the measured $I$ – $V$ data of the InGaAs HEMT devices with gate lengths from 30 to 130 nm and Si extremely thin silicon on insulator devices with gate lengths from 30 to 50 nm. We also discuss why at the expense of some physical rigor the basic MVS model can fit more simply the experimental data (except for the degradation in transconductance under high drain currents).

Modelling effect of parasitics in plasmonic FETs

The terahertz SPICE FET model has been experimentally validated in Si CMOS and InGaAs HEMTs up to 4.5 THz and updated to account for parasitic gate fringing capacitance and parasitic source and drain resistance. The model is in good agreement with experimental data at low and high THz field intensities. We also show that introducing additional capacitances linking the drain and gate electrodes may lead to enhancement of the THz plasmonic detector response at lower THz frequencies. The simulation results of the plasmonic detector response to a single terahertz pulse are in good agreement with our measured data.

Development of AlAsSb as a barrier material for ultra-thin-channel InGaAs nMOSFETs

ABSTRACTWe investigated AlAs0.56Sb0.44 epitaxial layers lattice-matched to InP grown by molecular beam epitaxy (MBE). Silicon (Si) and tellurium (Te) were studied as n-type dopants in AlAs0.56Sb0.44 material. Similar to most Sb-based materials, AlAs0.56Sb0.44 demonstrates a maximum active carrier concentration around low-1018 cm-3 when using Te as a dopant. We propose the use of a heavily Si-doped InAlAs layer embedded in the AlAsSb barrier as a modulation-doped layer. The In0.53Ga0.47As/AlAs0.56Sb0.44 double heterostructures with a 10 nm InGaAs well show an electron mobility of about 9400 cm2/V・s at 295 K and 32000 cm2/V・s at 46 K. A thinner 5 nm InGaAs well has an electron mobility of about 4300 cm2/V・s at 295 K. This study demonstrates that AlAs0.56Sb0.44 is a promising barrier material for highly scaled InGaAs MOSFETs and HEMTs.

Quantum well engineering of InAlAs/InGaAs HEMTs for low impact ionization applications

The performance of InAlAs/InGaAs quantum well field effect transistors are subject to high impact ionization and band-to-band tunneling (BTBT) due to its narrow bandgap feature. In this work, the energy gap is engineered using strain and quantization techniques to increase the effective energy gap leading to low impact ionization and BTBT leakage current. It is shown that the impact ionization is reduced in 5 nm channel device as compared to 13 nm device with onset at approximately Egeff/q. Also the band-to-band-tunneling current is reduced due to the increase in effective energy gap. We have also investigated the effects of quantum well engineering on the dc performance of InGaAs HEMTs.

Plasma Enhanced Terahertz Rectification and Noise in InGaAs HEMTs

In this work, we explore high frequency collective phenomena present in InGaAs HEMTs which lead to a peak in the current noise spectrum and enhance their DC response to THz signals, thus originating a resonance in the rectification of AC signals. These phenomena have been evidenced in recent experiments, in which THz detection as a result of plasma wave resonances has been demonstrated. In this paper, by means of Monte Carlo simulations, the noise spectra and the AC-DC rectification properties of the devices have been calculated and linked to the properties of the plasma oscillations within two distinct parts of the source-gate region: the capped and the recessed sections of the channel.

Investigation of high-frequency small-signal characteristics of FETs/HEMTs

Hydrodynamic calculations of the components of small-signal admittance and impedance matrix are performed for InGaAs HEMT. Modifications of high-frequency small-signal response spectra in going (i) from ungated to gated structures and (ii) from a thermally equilibrium state without a stream to a nonequilibrium state with the stream of carriers in the FET/HEMT channel are considered. The main attention is paid to the spectral behaviour of the admittance and impedance in the THz frequency range related to the excitation of 2D and 3D plasma oscillations in the gated and ungated regions of the conducting channel of FET/HEMT, respectively. Accompanied effects related to plasma phenomena such as the competition of 2D and 3D plasma oscillations, amplification of 3D and Dyakonov–Shur instability of 2D plasma oscillations and resonant detection of external THz action are discussed.

THz Emission Induced by an Optical Beating in Nanometer-Length High-Electron-Mobility Transistors

Experimental results of direct measurement of resonant terahertz emission optically excited in InGaAs HEMT channels are presented. The emission was attributed to two-dimensional plasma waves excited by photogeneration of electron–hole pairs in the HEMT channel at the frequency of the beating of two cw-laser sources. The presence of resonances for the radiation emission in the range of f0±10 GHz (with f0 from 0.3 up to 0.5 THz) detected by a Si-bolometer is found. The intensity of THz emission exhibits a nonlinear growth with increase of the pumping power.

InGaAs HEMT with InAs-rich InAlAs barrier spacer for reduced source resistance

An InAlAs/InGaAs HEMT with an InAs-rich barrier spacer (In0.52Al0.48As) to reduce the parasitic resistance is reported. Devices were obtained with a source resistance of 170 Ω-μm. A 40 nm gate length In0.7Ga0.3As HEMT with Lside=100 nm and tins=10 nm shows excellent transconductance and subthreshold characteristics including gm=1.6 mS/μm, DIBL=122 mV/V and S=80 mV/dec at VDS=0.5 V. In addition, this device exhibits an fT=530 GHz and fmax=445 GHz at VDS=0.7 V. These excellent characteristics mainly arise from a reduction in the source resistance through the use of the InAs-rich InAlAs spacer.

Aspect Ratio Impact on RF and DC Performance of State-of-the-Art Short-Channel GaN and InGaAs HEMTs

We report a comparison between state-of-the-art GaN and InGaAs HEMTs in terms of the minimum aspect ratio required to limit short-channel effects. DC and RF simulations were carried out through our full-band cellular Monte Carlo simulator, which includes the full details of the band structure and the phonon spectra. Our results indicate that the minimum aspect ratio for GaN devices is 15 for negligible short-channel effects and 10 for reduced short-channel effects. On the other hand, InGaAs devices perform well for lower aspect ratio values such as 7.5 and 4-5 for negligible and reduced effects, respectively. The origin of this difference between GaN and InGaAs HEMTs is believed to be related to the different dielectric constants of the two materials and the corresponding difference in the electric field distributions related to short-channel effects.