Influence Of Parasitic Capacitance Research Articles

Design and fabrication of integrated negative feedback resistor for InGaAs/InP avalanche photodiode

The serial resistor of alloy material can be integrated on negative feedback avalanche diodes to reduce afterpulsing effect. In this work, the influence of parasitic capacitance on the avalanche quenching resistor was theoretically analyzed. By using simulation model of device & circuit mixed-mode, the quenching capability of integrated resistors was evaluated with the parasitic parameters. For the material growth of feedback quenching resistor, thin film based on CrSi alloy was prepared by ion beam sputtering process, realizing the sheet resistance of 3 kΩ/square. The resistor material were sufficiently investigated by characterizing the morphology and element component. CrSi pattern of spiral shape was fabricated on sapphire substrate, realizing a resistor of the order of 500 kΩ in area of diameter 40 μm, which was equivalent to the active area of avalanche diodes. The electrical measurement indicated the excellent temperature stability of this integrated resistor, showing the promising application prospect for preparing high-performance negative feedback avalanche diodes.

Influence of Parasitic Capacitance on Turn-Off Current and Its Optimization Method for Transient Electromagnetic System

Influence of Parasitic Capacitance on Turn-Off Current and Its Optimization Method for Transient Electromagnetic System

Influence of Parasitic Elements and Operating Conditions of Semiconductor Switches on Power Losses and the Junction Temperature of These Switches

This article presents the results of computer analysis of selected switching networks. In these analyses, the influence of selected parasitic components of electronic switches on the total and active power losses in these switches is considered. Analyses are performed using the SPICE software for two models of semiconductor switches: an ideal switch with RC parasitic components and the SPICE model of an IGBT. The influence of parasitic capacitances and resistances of these devices operating with the control signal of different parameters values on the total and active power dissipated in these switches is analyzed. On the basis of the obtained computations the average and peak-to-peak values of the junction temperature of electronic switches at the steady state are calculated using a compact thermal model. It is shown that parasitic elements visibly influence waveforms of the active and total power. It is proved that the simplified model using the total power in computations of the junction temperature makes it possible to obtain a high accuracy of computations only in a situation when the transistor operates with a resistive load. For an inductive load, such simplification can cause an unacceptably high computation error exceeding even 30%. Such an error is a result of big differences between the active and total powers during switching-on and switching-off processes.

A Multi-Segment Compensation Method for Improving Power Density of Long-Distance IPT System

Inductive power transmission has been applied in industries, such as electric vehicles, consumer electronics and biomedical fields. However, there is a long-term key problem in this field that has not been solved. This is the adverse effect of the parasitic capacitance of the coil, which will cause the change of the coil inductance, the reduction of the quality factor and the reduction of efficiency. Especially in the field of long-distance wireless power transmission. The existing technologies all adopt the scheme of sacrificing volume in exchange for the quality factor of the coil. As a result, the volume of the system is very large, and the quality factor of the coil is still not high enough because the influence of parasitic capacitance has not been completely eliminated. Here, we found the solution. Connect compensation capacitors in series to the coil sections to short-circuit the parasitic capacitance and reduce its loss. The designed system has a diameter of 502 mm and a thickness of 22 mm, which can transmit 115.2 W of power within a distance of two meters with an efficiency of 29%.

An Adaptive Switching Control Strategy under Heavy–Light Load for the Bidirectional LLC Considering Parasitic Capacitance

The LLC topology is widely used to link renewable energy and inverters to provide constant voltage in the smart grid. Due to its characteristics, the voltage regulation range under light load conditions is limited, so that the output voltage cannot be maintained constant. The adaptive switching control strategy is proposed in this paper to keep the output constant. Under heavy load conditions, the voltage is kept constant by adjusting the frequency to ensure the accuracy of the control. The phase shift is adjusted to achieve constant voltage, considering the influence of parasitic capacitance on the modeling process for the changing trend of output voltage in light load conditions. The switching point is calculated from the characteristic curve to ensure that the output voltage is stable during mode switching. In addition, there is a new hysteresis control which is robust near the switching point to cope with the instability of the new energy itself and frequent disturbance under light load. Finally, a 400V–36V–1KW prototype is used to verify this control strategy.

Parasitic Capacitance Effects on Active Clamp Flyback Output Characteristics: Application to IPOP Connection

Different mechanisms for balancing power between parallel connected modules have been presented in recent years. They have been broadly classified into active and passive methods. The high output impedance of topologies, including active clamp networks, suggests that they can achieve output current sharing passively when they are connected in parallel. However, some parasitic elements, such as stray capacitances and leakage inductances, have not been considered in the theoretical analyses. Moreover, these need to be taken into account when a high step-up ratio is required because they modify the behavior and output impedance of a module, which changes the current balance. This paper presents a detailed analysis of the influence of parasitic capacitances on active clamp flyback converters that were parallel connected, using the output impedance as a current self-balance method. The proposed solution to alleviate the negative effects on current balance was also studied and validated as a successful method that did not increase the complexity of the controller. Finally, the results that were obtained using an experimental prototype with two 100W modules helped to verify the theoretical results.

Influence of MOSFET Parasitic Capacitance on the Operation of Interleaved ZVS Boost Converters

Interleaved zero-voltage switching boost converters have been known for over 20 years. However, the influence of parasitic capacitance of transistors has not been described. In this paper the converter is analyzed and the equation for voltage ratio is derived for any number of converter phases. First a general description of the topology, including main voltage and current waveforms, is provided. Subsequently the converter is analyzed and conditions for soft switching are derived. Next the analysis results are compared to measurements of an experimental converter setup. Discrepancies are identified and the influence of parasitic capacitance is analyzed. By considering the parasitic capacitance the difference between experimental and analytical results of voltage ratio is reduced from 0.2 to less than 0.05.

Improvement of the microcapacitive humidity sensor by the package optimisation

To achieve good properties such as the hysteresis, repeatability, stability, linearity and response time in this work, the optimisation processes of the package are presented for a microcapacitive humidity sensor. On the basis of theoretical analysis, the optimisation will be conducted in two ways, including reducing the effect of parasitic capacitance in the microcapacitive humidity sensor measurement system and decreasing the adsorption of water molecules on the package surface. The reduction of the influence of parasitic capacitance was realised by reasonably designing the PCB and the isolation package. The decrease of water adsorption on the package surface was achieved by coating a layer of hydrophobic material. The experimental results proved that the package optimisation enables the humidity sensor with better performance; for instance the hysteresis error is more than six times lower, the repeatability error is more than ten times lower, and the temperature drift is about two times lower, and the linear fitting error is three times lower than the pre-optimised humidity sensor. Especially, the humidity response time in both adsorption and desorption is extremely improved.

An Automotive Low-Power EMC Robust Brokaw Bandgap Voltage Reference

This article proposes an electromagnetic compatibility improved bandgap voltage reference with a low current consumption of only 3.5 μA in an automotive environment with a wide temperature range from –40 °C to 160 °C and a high electromagnetic interference (EMI) robustness. The proposed reference is based on the well-known Brokaw bandgap with only five bipolar transistors in the bandgap core including collector current leakage compensation. We analyzed parasitic effects in the bandgap core such as the influence of parasitic capacitances between the substrate and the collectors of these bipolar transistors as well as the impact of the operational amplifier. We made recommendations on how to improve the bandgap EMI robustness. Simulation results were compared with measurements on a test chip. The measurement results showed excellent EMI robustness.

Thermal Performance and Reliability Analysis of a Medium-Voltage Three-Phase Inverter Considering the Influence of High $dv/dt$ on Parasitic Filter Elements

In recent years, the use of silicon carbide (SiC) power semiconductor devices in medium-voltage (MV) applications has been made possible due to the development of high blocking voltage (10–15 kV)-based devices. While the use of these devices brings in a lot of advantages, the semiconductor devices are exposed to high peak stress (of up to 15 kV) and a very high $dv/dt$ (of up to 100 kV/ $\mu \text{s}$ ). The high $dv/dt$ across the devices leads to a high $dv/dt$ across other components connected to the system. This makes the effect of the parasitic capacitance across the components to be of paramount importance since an additional current flows through the components and, consequently, through the switching device. This additional current flows during each switching transition and leads to increased switching losses in the device. This article analyzes the effect of these additional losses on the lifetime of the device. The thermal performance of a three-phase inverter power block is provided, and a mission profile (solar irradiance and temperature)-based analysis is carried out to account for the additional junction temperature rise. The rainflow counting method is implemented to identify the mean and amplitude of each thermal cycle. An empirical device lifetime model is used to calculate the number of cycles to failure. Finally, the Palgrem Miner rule is used to quantify the total damage in the device. Comparisons have been carried out on basis of lifetime for both the cases (with and without the influence of parasitic capacitances). This analysis can be helpful in validating the importance of the design of filter inductors in these MV applications.

A systematic study of device structure on DC and small‐signal characteristics of millimeter‐wave AlGaN/GaN HEMT

AbstractIn this paper, the relationship between the gate structure, passivation structure, short‐channel effect, source‐drain distance, DC, and the small‐signal characteristic of a device is studied through simulations. By studying the gate structure and passivation layer, it is concluded that the operating frequency of a device increases as the gate length decreases. However, as the gate length decreases, the gate resistance becomes the main factor restricting the small‐signal performance. In order to solve the contradiction between the gate resistance and gate length, a T‐shaped gate structure is studied, in which the gate height, gate cap, and passivation layer thickness are optimized. It is found that when the gate height and gate cap are 120 and 500 nm, respectively, the parasitic capacitance introduced by the gate cap can be minimized. Meanwhile, the influence of gate resistance on the small‐signal gain can also be reduced. Besides, the short‐channel effect is analyzed, and the scheme for improving the short‐channel effect is proposed. By analyzing the source‐drain distance, and considering the influence of parasitic capacitance and resistance on the small‐signal characteristic, the gate‐source spacing is determined to be 0.9 μm. The design of a gate‐drain spacing is mainly based on the influence of a breakdown voltage; therefore, the gate‐drain spacing should be 1.5 to 2 μm.

Performance of the COMPASS II shashlyk calorimeter ECAL0 read out by SiPMs

Abstract The matrix of 3 × 3 modules of the EM calorimeter ECAL0 (COMPASS II) read out by MPPC S12572-010P SiPMs with the pixel density of 10 4 mm −2 and an area of 3 × 3 mm 2 is studied in the range of electron energies 1–30 GeV. It is observed that the MPPC has additional response nonlinearity and a significantly smaller dynamic range of output signals than expected. The influence of parasitic capacitance between pixels on the pixel gain is discussed and proposed as explanation. The energy resolution of the calorimeter is measured to be σ E ∕ E = 7 . 1 % ( 1 + 0 . 06 ∕ E ) ∕ E ⨁ 1 . 4 % E 0 . 25 , where electron energy E is given in GeV.

Modeling, Analysis, and Implementation of High Voltage Low Power Flyback Converter Feeding Resistive Loads

In High Voltage flyback converters, the dominant factor that influences a converter operation is the parasitic capacitance. A significant portion of input energy is utilized in charging the parasitic capacitances of the circuit, which is circulated back to the source at the end of every switching cycle. The circulating energy is a function of output voltage, load power, and parasitic capacitances and remains significant in High Voltage Low Power (HVLP) applications. This energy transfer phenomenon involving parasitic capacitances results in a reduced fraction of input energy reaching the load in every cycle, thereby resulting in an apparent deviation in the converter operating point compared to ideal flyback in case of resistive loads. An analytical energy-based model is derived, which includes the effect of parasitic capacitances, and is valid for steady state and dynamics of HVLP flyback converters feeding resistive loads. The influence of parasitic capacitances on the switch voltage of the converter is exploited to achieve Zero Voltage Switching (ZVS), thereby minimizing the turn- on loss. The proposed analytical model is verified through simulation and experimental results on 1.5 kV/ 5 W and 1.5 kV/ 200 mW resistive loads.

Photoelectric Response in Indium-Tin Oxide Films

In this paper, the mechanism of photoelectric response of indium tin oxide films is discussed. We observed the photoelectric emission in indium tin oxide films and suggested the physical mechanism describing the photoelectric response based on this phenomenon. We showed that the anisotropy of the electric field could be associated with preferred orientation of the grains in deposited films. We discussed the influence of parasitic capacitance on the shape of the photoelectric response. In this paper, we showed that photoelectric effect in indium-tin oxide films could be applied to measure the temporal characteristics of the laser pulse.

Influence of Parasitic Capacitance on Single and Dual 2-D Magnetic Recording Read Head Performance

The parasitic capacitance of the reader affects performance through signal-to-noise ratio (SNR) in single readers and through crosstalk in dual 2-D magnetic recording readers. In a single reader, the majority of the capacitance is not from shield-to-shield capacitance but instead from lead-to-shield capacitance. The low-pass filtering of the reader circuit leads to an equalized SNR that depends on the parasitic capacitance. In a dual reader, the capacitance between the outer shields must be considered in addition to the capacitance between the inner shields in order to model accurately the crosstalk. Finite-element electromagnetic models and lumped element circuit models are validated with RF experiments on real heads.

Extraction of Trap Densities in Amorphous In-Ga-Zn-O Thin-Film Transistors by Using Efficient Surface Potential Calculations

A novel extraction method for trap densities in amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) is developed. In this method, a new calculation procedure for efficiently determining surface potentials (SPs) in the a-IGZO layer is used with low-frequency capacitance-voltage ( $C$ - $V$ ) measurements. To enhance the computational efficiency of the extraction method, we propose an approximate expression relating the front-side and back-side SPs, so that it is possible to determine SPs without conventionally required calculation steps, such as either meshing the a-IGZO layer or calculating the potential profiles for the entire layer. The extraction method is tested by using low-frequency $C$ - $V$ curves of a self-aligned a-IGZO TFT to minimize the influence of parasitic capacitances and resistances. This method is expected to facilitate the extraction of trap densities, and contribute to characterization and modeling of a-IGZO TFTs.

The Research on MEMS Micro Capacitance Sensor Detection Based on MS3110

A universal capacitive readout integrated circuit MS3110 is used to measure capacitances in micro capacitance sensor. The configuration, operating principle and process of MS3110 are introduced and a method of programming the inner register on-chip with STM32 is presented with the control block diagram. Performance of MS3110 has been tested by the inner adjust capacitance. A comb micro accelerometer is designed and manufactured. A tentative equivalent electric model of accelerometer is built according to a series of capacitance tests, and the influence of parasitic capacitance in accelerometer system is discussed.

Piezoelectric MEMS resonator-based oscillator for density and viscosity sensing

The resonant characteristics of a mechanical resonator immersed in liquid provide valuable parameters for density and viscosity sensing. In particular, the combination of microresonators with electronic circuits, for tracking their natural frequency and quality factor, has great interest as low cost and size solution. In this work, we focus on an oscillator featuring an in-liquid piezoelectric microplate resonator as the frequency-selective element. Specifically, by selecting the second-order bending mode in the length-direction, a reliable oscillator operation, for a range of liquid properties, was achieved at moderate frequency. Besides, the out-of-plane vibration allowed for both density and viscosity to be deduced separately. The influence of parasitic capacitances in the device response has been identified as the major difficulty for the realization of the oscillator circuit. To minimize this effect, a compensation method based on a non-released reference device and an instrumentation amplifier was implemented, which resulted in a clear resonance with low baseline and high phase step. In a first test with the resonator immersed in isopropanol, the circuit generated a stable wave with an Allan deviation of 2.32·10−7, improving by one order of magnitude the only published value, to the authors knowledge, for a comparable device in liquid. An alternative tracking system, based on digital phase-locking benchtop instrumentation, was tested with the same resonator, showing a comparable stability (2.35·10−7) and supporting our approach. Finally, the operation of the system as a sensor was demonstrated. After a calibration process, the density and viscosity of eight test liquids could be compared to measurements with a commercial instrument, showing differences lower than 0.4% in density and 8% in viscosity. The minimum detectable changes were also evaluated, being 4.09·10−6g/ml for the density and 2.07·10−3mPas for the viscosity, both for a viscosity of 7.36mPas at 10 samples per second.

Solid-State Bipolar Marx Modulator Modeling

A mathematical model that simulates the operation of a solid-state bipolar Marx modulator topology, including the influence of parasitic capacitances is presented and discussed as a tool to analyze the circuit behavior and to assist the design engineer to select the semiconductor components and to enhance the operating performance. Simulations show good agreement with experimental results, considering a four stage circuit assembled with 1200 V isolated gate bipolar transistors and diodes, operating at 1000 V dc input voltage and 1-kHz frequency, giving 4 kV and 10-μs output pulses into several resistive loads. Results show that parasitic capacitances between Marx cells to ground can significantly load the solid-state switches, adding new operating circuit conditions.

Outer Conductor Inner Diameter Measuring System of Coaxial Transmission Line

In this paper, an outer conductor diameter measuring system for coaxial transmission lines are introduced. The structure of pole-distance changing cylinder capacitor sensor probe aperture measuring is analyzed. The signal analysis and control system of the whole measurement system is introduced in detail. The guarding ring technology is used to eliminate edge effect of effective measuring sensor electrode. The operation amplifying transform circuit is used to overcome the nonlinear problem of pole-distance changing sensor. Driving cable technology is adopted to reduce the influence of parasitic capacitance. Through the CCD image centering and grating encoder driven by stepping motor drive system and encoder system X, Y, Z axis precision positioning, in order to realize the long hole in any section of the nanomeasuring diameter; The measuring types of this system is: Φ 0.8 mm, Φ 1 mm, Φ 1.8 mm to Φ 7 mm hole diameter. The resolution is 5nm--20nm, the standard deviation of repeated measurement is 0.05μm--0.1μm. The measurement uncertainty is 2μm0.2μm.