Industrial Hardware Design Research Articles

Hardware Trojan detection via rewriting logic

Hardware security studies, discovers, and classifies hardware attacks as well as defense strategies such as prevention and protection methods along the entire hardware production chain. Hardware Trojans represents a hardware attack model that emerged in the last decades in the hardware security community. In this paper, we present a methodology for achieving a scalable approach to detect hardware Trojans at the design stage using program transformation in a rewrite-based environment. We note that the hardware Trojan attack considered here assumes the vulnerability introduction during the hardware design stage while the payload is obtained as information leakage during the hardware usage. The main contribution in our work is the methodology correctness proof for a high security evaluation assurance level. We also benchmark the effectiveness of our methodology on industrial hardware designs, e.g., Advanced Encryption Standard cores, which is widely used and deployed for numerous devices and applications.

Stress-Crack detection in maize kernels based on machine vision

Stress-crack detection is important for determining seed quality. This paper presents both a machine-vision-based method and a prototype of an industrial hardware design for stress-crack detection in maize kernels. Specifically, we present a cascade model incorporating kernel-status classification, region-of-interest segmentation, and crack-detection models. The status-classification model selects kernels with the correct camera orientation, whereas the region-of-interest segmentation model locates the main axis of the kernel and supplies a kernel mask for endosperm segmentation. Further, we utilise the EDLines algorithm to detect cracks and apply three novel constraints to distinguish real cracks from noise. The results of experiments conducted indicate that our integrated hardware–software system can detect stress cracks in maize kernels effectively and automatically. The observed precision and recall of the overall system were 92.7% and 94.4%, respectively.

Design Automation of Neural Network Applications Using Formal Techniques—Rapid Prototyping Using the CCC Synthesizer

Cellular neural network (CNN) implementations used in real time image processing are rapidly generated by a formal High-level synthesis (HLS) toolset in this work. Industrial and academic hardware design projects can benefit from the use of the Custom Coprocessors Compilation (CCC) HLS behavioral synthesise, via the massive reduction in design and verification time. The CCC tool is built with formal compiler-compiler, Logic Programming and XML validation techniques, thus the generated RTL VHDL or Verilog models are provably-correct. In this work, we rapidly modeled CNNs in the ADA programming language, compiled and verified along with all the necessary testbenches in GNU ADA. Edge-detection, halftoning and morphological processing applications were prototyped, so as to evaluate the CCC HLS method, which was the main contribution of this work. The combination of Logic Programming and RDF validation techniques, as well as prototyping of CNN applications made this work unique.

A Multilevel Memetic Algorithm for Large SAT-Encoded Problems

Many researchers have focused on the satisfiability problem and on many of its variants due to its applicability in many areas of artificial intelligence. This NP-complete problem refers to the task of finding a satisfying assignment that makes a Boolean expression evaluate to True. In this work, we introduce a memetic algorithm that makes use of the multilevel paradigm. The multilevel paradigm refers to the process of dividing large and difficult problems into smaller ones, which are hopefully much easier to solve, and then work backward toward the solution of the original problem, using a solution from a previous level as a starting solution at the next level. Results comparing the memetic with and without the multilevel paradigm are presented using problem instances drawn from real industrial hardware designs.

Advanced verification by automatic property generation

Property checking is a promising approach to prove the correctness of today's complex designs. However, in practice this requires the formulation of formal properties, which is a time consuming and non-trivial task. Therefore, the acceptance and efficiency of formal verification techniques is increased by an automated support for formulating design properties. The authors propose a new methodology to automatically generate complex properties for a given design. The tool ‘Dianosis’ (Dynamic Invariant Analysis on Simulation Traces) implements this methodology by analysing a simulation trace and extracting properties. Complex properties describe the abstract design behaviour and improve design understanding, for example by discussing them with the particular designers or reflecting them to the specification. The properties are presented in a format that is easy to read and they can be used as a basis for the application of formal or assertion-based verification techniques. We provide experimental results on industrial hardware designs that show the effectiveness of ‘Dianosis’ and motivate the practical use.

The line segment table: a fast region description algorithm

In this paper a new fast region description method named line segment table is proposed. Each element in the table represents a horizontal line, which includes the coordinates of a line segment, the relationship between upper and lower lines, and the characteristics of a line. Thus a segment table can be used to describe the shape of a region precisely. This paper shows that these regional operations can be decomposed into a set of union operations of the corresponding components of all horizontal lines. Thus the resource intensive regional operations can be turned into combinations or truncations of the line segments. This paper also presents a set of line processing operations, which can be applied in binary image processing such as erosion, dilation, convolution and correlations. Line segment encoding is particularly applicable to line-based processing. Furthermore it is also useful for applications such as seed filling. This paper proposes a fast bucket sorting algorithm which is faster than traditional contour tracing algorithms and seed filling algorithms. This algorithm simplifies regional processing and improves processing efficiency, and is particularly advantageous in the application of industrial real-time detection and hardware design.

Formal verification of a SONET data stream processor

We describe the formal verification of an industrial hardware design from PMC-Sierra, Inc. The design under investigation is a telecom system block, which processes a portion of the synchronous optical network (SONET) line overhead of a received data stream. We adopted a hierarchical modelling and verification approach which follows the natural design hierarchy. The formal specification and verification have been carried out based on multiway decision graphs (MDG), a new decision diagram subsuming the traditional binary decision diagrams and allowing abstract data and functions. The verification has been performed using both equivalence and model checking. To measure the performance of the MDG-based model checking, we also conducted a comparative verification of the same design using Cadence FormalCheck.