Industrial Chips Research Articles

Performance of a mobile mechanical screen to improve the commercial quality of wood chips for energy

The study analyzed the performance of a mobile screening device for upgrading coarse wood chips to residential user standards, by removing oversize particles and fines. The machine was designed for transportation to forest landings, logistic terminals and plant chip yards. Average productivity was 1.9 oven-dry tons (odt) h−1, corresponding to a screening cost of 28.5€odt−1. This figure was lower than the price increase obtained by upgrading industrial chips to residential user standards. Hence, screening offered a profit of 4.7€odt−1, or 16% of the original screening cost. The screening process was capable of upgrading chips from industrial to residential specifications, by reducing the incidence of oversize particles below the 1% critical threshold. Screening also allowed a substantial reduction in the content of fines. A similar effect was not verified for crushed wood, which failed to meet the specifications for residential fuel.

Faster min–max resource sharing in theory and practice

We consider the (block-angular) min–max resource sharing problem, which is defined as follows. Given finite sets $${\mathcal{R}}$$ of resources and $${\mathcal{C}}$$ of customers, a convex set $${\mathcal{B}_c}$$ , called block, and a convex function $${g_c:\mathcal{B}_c\to\mathbb{R}_{+}^{\mathcal{R}}}$$ for every $${c\in\mathcal{C}}$$ , the task is to find $${b_c\in\mathcal{B}_c\ (c\in\mathcal{C})}$$ approximately attaining $${\lambda^*:=\inf\{\max_{r\in\mathcal{R}}\sum_{c\in\mathcal{C}}(g_c(b_c))_r \mid b_c\in\mathcal{B}_c\ (c\in\mathcal{C})\}}$$ . As usual we assume that g c can be computed efficiently and we have a constant σ ≥ 1 and oracle functions $${f_c : \mathbb{R}_{+}^{\mathcal{R}} \rightarrow \mathcal{B}_c}$$ , called block solvers, which for $${c \in \mathcal{C}}$$ and $${y \in \mathbb{R}_{+}^{\mathcal{R}}}$$ return an element $${b_c \in \mathcal{B}_c}$$ with $${y^{\scriptscriptstyle\top}{g_c(b_c)} \leq \sigma \inf_{b \in \mathcal{B}_c} y^{\scriptscriptstyle\top}{g_c(b)}}$$ . We describe a simple algorithm which solves this problem with an approximation guarantee σ(1 + ω) for any ω > 0, and whose running time is $${O(\theta(|\mathcal{C}|+|\mathcal{R}|) \log|\mathcal{R}|(\log\log|\mathcal{R}|+\omega^{-2}))}$$ for any fixed σ ≥ 1, where θ is the time for an oracle call. This generalizes and improves various previous results. We also prove other bounds and describe several speed-up techniques. In particular, we show how to parallelize the algorithm efficiently. In addition we review another algorithm, variants of which were studied before. We show that this algorithm is almost as fast in theory, but it was not competitive in our experiments. Our work was motivated mainly by global routing in chip design. Here the blocks are mixed-integer sets (whose elements are associated with Steiner trees), and we combine our algorithm with randomized rounding. We present experimental results on instances resulting from recent industrial chips, with millions of customers and resources. Our algorithm solves these instances nearly optimally in less than two hours.

Modeling of Alkali Impregnation of Eucalyptus Wood

In wood pulping processes, the quality of the impregnation stage has a significant influence on the final pulp properties. In this work, a refined version of a previously published model is used to analyze this operation stage. For liquor containing NaOH and Na 2 S, the study considers the reaction of wood acetyls and acidic groups. The Donnan effect is applied for analysis of ion concentrations in the wood-liquid interphase. The predicted concentration profiles are in acceptable agreement with the experimental results. The model is used afterward to simulate a batch or a cocurrent continuous kraft impregnation process. In the impregnating liquor, the alkali concentration is gradually reduced due to chemical reactions and alkali accumulation in the wood chips. The level of impregnation is finally analyzed considering different chip thickness values corresponding to an industrial chip stock sample.

Analyzer allows testing of polar response patterns of directional hearing aids

Analyzer allows testing of polar response patterns of directional hearing aids

WOOD WASTE CHARACTERIZATION FOR COMPOSTING

Use of composted wood wastes has beneficial effects on soil physical and chemical conditions and on crop productivity. This paper includes compositional data from thirteen different wood industry wastes, including bark, chips, and sawdust from three Eucaliptus, Populus, and Salicaceae species, hardboard dust, mud from paper industry and raw cork. Particle size, pH and conductivity on the 1:10 waste:water extract, organic matter (ignition), organic C, total N, N-N0 3 , N-NH 4 , total Ca, Mg, K, Na, Cu, Mn, P, and Zn were determined. The C:N ratio was high in all of the materials (69 to 358), suggesting that it would be necessary to add N to help microorganisms to decompose the wastes. All wastes showed low N-NH 4 , P, Mg, K and Na content. N-NO varied from 259 to 829 ppm, with hardboard dust and mud from paper industry showing the highest values. Ca content was highest in the bark of the three species (1.91 to 5.60%). Cu content was highest (132 ppm) in mud from paper industry, while Zn was highest in the bark of Salicaceae species. The bark of Eucaliptus rostrata Schlecht and Eucaliptus saligna Smidth showed acceptable Mn content. This study shows that the different wood wastes tested are promising materials for composting and use in intensive cropping soils.

Energy and exergy analyses of an industrial wood chips drying process

In this study, a comprehensive thermodynamic investigation through energy and exergy analyses is conducted to assess the performance of an industrial chips drying process and study how its operating conditions and efficiency can be improved further. In this regard, energy and exergy efficiencies are evaluated with the actual thermodynamic data available, as obtained from the factory, in Turkey. Energy and exergy efficiencies of the drum drying system (DDS) are found as 34.07% and 4.39%, respectively. The analysis results show that exergy efficiency is less than energy efficiency. The main reason of this low exergy efficiency for this drying process is high exergy destruction, as 41.5% of input exergy value. Energy can be recovered via an economizer from hot moist air leaving from the system. If stack gas temperature decreases from 130 to 90°C, regain energy and exergy values are to be 51 976 and 8162 kW, respectively. These recovered potentials can be used for district heating system in winter season and for district cooling system in summer season by using absorption cooling system. Energy and exergy efficiency values can be increased to 93.15 and 43.08%, respectively, by incorporating a heat exchanger into the system. Copyright The Author 2009. Published by Oxford University Press. All rights reserved. For Permissions, please email: journals.permissions@oxfordjournals.org, Oxford University Press.

A generalization of Dijkstra's shortest path algorithm with applications to VLSI routing

We generalize Dijkstra's algorithm for finding shortest paths in digraphs with non-negative integral edge lengths. Instead of labeling individual vertices we label subgraphs which partition the given graph. We can achieve much better running times if the number of involved subgraphs is small compared to the order of the original graph and the shortest path problems restricted to these subgraphs is computationally easy.As an application we consider the VLSI routing problem, where we need to find millions of shortest paths in partial grid graphs with billions of vertices. Here, our algorithm can be applied twice, once in a coarse abstraction (where the labeled subgraphs are rectangles), and once in a detailed model (where the labeled subgraphs are intervals). Using the result of the first algorithm to speed up the second one via goal-oriented techniques leads to considerably reduced running time. We illustrate this with a state-of-the-art routing tool on leading-edge industrial chips.

Verification of a network ASIC Component using Bounded Model Checking

Recently, a new technique called bounded model checking has been proposed that uses fast satisfiability solvers instead of binary decision diagrams (BDDs). This paper presents the experiences on formally verifying the behaviour and implementation of an Asynchronous Transfer Mode (ATM) network switching module using Nusmv2 tool. A number of properties described by linear temporal logic (LTL) are provided, and their verification in reasonable central processing unit (CPU) time is accomplished by estimating a more precise bound k which is determined by the circuit structure. Moreover, equivalence checking between the structural and behavioural descriptions of the whole switch module as one model is performed, and the results compared with those of the BDD-based approach. Based on that experience, bounded model checking will be the mainstream of industrial chip verification.

A Structure Preserving Index Reduction Method For MNA

AbstractTransient analysis in industrial chip design leads to very large systems of differential‐algebraic equations (DAEs). The numerical solution of these DAEs strongly depends on the so called index of the DAE. In general, the higher the index of the DAE is, the more sensitive the numerical solution will be to errors in the computation. So, it is advisable to use mathematical models with small index or to reduce the index.This paper presents an index reduction method that uses information based on the topology of the circuit. In addition, we show that the presented method retains structural properties of the DAE. (© 2006 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Analysis and methodology for multiple-fault diagnosis

In this paper, we propose a multiple-fault-diagnosis methodology based on the analysis of failing patterns and the structure of diagnosed circuits. We do not consider the multiple-fault behavior explicitly, but rather partition the failing outputs and use an incremental simulation-based technique to diagnose failures one at a time. Our methodology can be further improved by selecting appropriate diagnostic test patterns. The n-detection tests allow us to apply a simple single-fault-based diagnostic algorithm, and yet achieve good diagnosability for multiple faults. Experimental results demonstrate that our technique is highly efficient and effective. It has an approximately linear time complexity with respect to the fault multiplicity and achieves a high diagnostic resolution for multiple faults. Real manufactured industrial chips affected by multiple faults can be diagnosed in minutes of central processing unit (CPU) time.

Guest Editor's Introduction: ITC Examines How Test Helps the Fittest Survive

The theme of the 2005 International Test Conference is “Test: Survival of the Fittest.” In conjunction with this year's ITC, this special section examines how test helps the fittest of the industry's chips, boards, and systems survive manufacturing to reach its customers. These articles discuss topics such as X-tolerant test response compaction, reducing yield loss using a constrained ATPG, and using IDDQ testing with today's high background currents.

Legalizing a Placement with Minimum Total Movement

Most tools for the placement of very large scale integrated chips work in two steps. First, the cells that have to be placed are roughly spread out over the chip area, ignoring disjointness (global placement). Then, in a second step, the cells are moved to their final position such that all overlaps are removed and all additional constraints are met (detailed placement or legalization). In this paper, we describe new ideas for legalization. We divide the task into appropriate subproblems that can be solved optimality in polynomial time. For the most important parts, even a linear running time can be shown. Together, the solutions of the subproblems can be combined to an algorithm that legalizes a placement minimizing the total (linear or squared) movement of cells. The algorithm is tested on a set of recent application specific integrated circuits and the results are compared to lower bounds showing that it computes provably good solutions (within a few percent of the optimum) even on very large industrial chips. By introducing significantly fewer violations, our legalization helps in overall design closure.

Design optimization of low-power high-performance DSP building blocks

In recent years, power dissipation along with silicon area has become the key figure in chip design. The increasing demands on system performance require high-performance digital signal processing (DSP) systems to include dedicated number-crunching units as individually optimized building blocks. The various design methodologies in use stress one of the following figures: power dissipation, throughput, or silicon area. This paper presents a design methodology reducing any combination of cost drivers subject to a specified throughput. As a basic principle, the underlying optimization regards the existing interactions within the design space of a building block. Crucial in such optimization is the proper dimensioning of device sizes in contrast to the common use of minimal dimensions in low-power implementations. Taking the design space of an FIR filter as an example, the different steps of the design process are highlighted resulting in a low-power high-throughput filter implementation. It is part of an industrial read-write channel chip for hard disks with a worst case throughput of 1.6 GSamples/s at 23 mW in a 0.13-/spl mu/m CMOS technology. This filter requires less silicon area than other state-of-the-art filter implementations, and it disrupts the average trend of power dissipation by a factor of 6.

Numerical Study on the Effect of Cross-Flow on Turbulent Flow and Heat Transfer Characteristics Under Normal and Oblique Semi-confined Impinging Slot Jets

Impinging jets are commonly used in industrial dryers and electronics chip cooling. Since in industrial practice it is necessary to use multiple jets, the interaction between jets can have important effect on their heat transfer performance. Hence, the study of cross-flow caused by the spent flow of upstream jets is obviously significant. In this study, a computational fluid dynamics simulation was carried out of the flow and heat transfer characteristics for a single semi-confined turbulent slot jet of air impinging normally or obliquely into an imposed air cross-flow of the same or different temperature. The standard k−ε and the Reynolds stress models were used. Effects of the various flow parameter (e.g., jet-to-cross-flow mass ratio) and geometric parameters (e.g., nozzle-to-target spacing and jet angle) were evaluated at a fixed Reynolds number (11,000 and 12,000) for equal and unequal temperatures of the jet and cross-flow. Results indicate the significant degradation of the impingement heat transfer rates due to cross-flow and a relatively minor influence of the temperature difference between the jet and cross-flow over the ranges of parameters studied. Both the turbulence models produced comparable Nusselt number distributions along the impingement surface.

Compositional Generation of MC/DC Integration Test Suites

We present a method for automatically generating tests for reactive systems specified by concurrently executing extended finite state machines. The generated test suites satisfy the modified condition/decision coverage criterion at unit and integration levels. The generation of MC/DC suites for eager first-order functional programs is subsumed. An industrial chip card case study illustrates the approach.

Present and Future Industrial Applications of Bio-Inspired VLSI Systems

Biology can be a rich source of inspiration for engineers. In particular, designers of VLSI processing circuits and systems can draw inspiration from several aspects of the brain. Inspired from evolution, the opportunistic exploitation of all the properties of the technology provides very efficient analog circuit techniques. The collective computation carried out by the brain in its massively parallel architecture can be emulated on silicon. Strategies like learning and adaptation are very beneficial to VLSI processing. The same is true for the unusual ways used by the brain to represent signals and information. Four industrial chips developed with this bio-inspired approach are described, as well as several experimental circuits that demonstrate its potential for future products.

Optimization of a wood chip refining process based on fuzzy relational models

The authors developed a fuzzy relational model for an industrial wood chip refining process. In conjunction with an optimization technique, this model is used either to minimize energy consumption of the refiner operation while maintaining pulp properties within acceptable limits, or to optimize the pulp properties within the refiner operation range. The model has been implemented in a western Canadian pulp and paper mill.

A timing analysis algorithm for circuits with level-sensitive latches

For a logic design with level-sensitive latches, we need to validate timing signal paths which may flush through several latches. We developed efficient algorithms based on the modified shortest and longest path method. The computational complexity of our algorithm is generally better than that of known algorithms in the literature. The implementation (CYCLOPSS) has been applied to an industrial chip to verify the clock schedules.

Redundancy analysis and removal for VLSI ASIC's

Due to high testcoverage requirements for VLSI ASIC designs the problem of untestable stuck-faults in the combinational logic of ASIC designs has recently gained growing attention. Some of those untestable faults are due to testgenerator deficiency, other untestable faults are due to redundant logic. We focus on this second class of untestable faults. This paper presents a technique for handling untestable faults, which are due to redundancies, in the process of testgeneration for chip designs. The aim is to remove as many as possible redundancies in the chip design before the actual testgeneration process starts. This enhances the testability of the design and shortens the CPU-time needed for the actual testgeneration. It may reduce the chip area (positive effect) and does not increase the static timing delay of the chip based on a longest path calculation (no negative effect). The proposed method is to restrict to subnetworks for redundancy removal. In this paper we explain how this method for analyzing and removing redundancies can be applied to industry chip designs and how it fits into the existing Electronic Design Automation (EDA) system in the Lab Böblingen. Finally experimental results for Böblingen IBM level sensitive scan designs (LSSD) and for the ISCAS '85 benchmark circuits [3] are reported.

Amazonian lignocellulosic materials-i fungal screening from decayed laurel and cedar trees

Fungi were screened for important industrial enzymes produced from industrial chips and sawdust of laurel (Louro inamui, Ocotea cymbarum) and cedar (Cedro, Cedrella odorata). Seven hyphomycetes and one zygomycete were isolated and characterized. Two different media for testing the enzymatic activities were used. In general, in potato dextrose (1%) medium (M-3) a preponderancy of ligninolytic over cellulolytic enzymes was observed. In potato infusion-sawdust wood (1%) medium (M-4) the cellulolytic, xylanolytic, and lipolytic enzymes were efficiently induced. Significant modulation of enzyme production by the carbon source was found in the extracted fungi from self-heated industrial chips piles of cedar and laurel trees at the Amazonian region.