Redundancy analysis and removal for VLSI ASIC's

Abstract

Due to high testcoverage requirements for VLSI ASIC designs the problem of untestable stuck-faults in the combinational logic of ASIC designs has recently gained growing attention. Some of those untestable faults are due to testgenerator deficiency, other untestable faults are due to redundant logic. We focus on this second class of untestable faults. This paper presents a technique for handling untestable faults, which are due to redundancies, in the process of testgeneration for chip designs. The aim is to remove as many as possible redundancies in the chip design before the actual testgeneration process starts. This enhances the testability of the design and shortens the CPU-time needed for the actual testgeneration. It may reduce the chip area (positive effect) and does not increase the static timing delay of the chip based on a longest path calculation (no negative effect). The proposed method is to restrict to subnetworks for redundancy removal. In this paper we explain how this method for analyzing and removing redundancies can be applied to industry chip designs and how it fits into the existing Electronic Design Automation (EDA) system in the Lab Böblingen. Finally experimental results for Böblingen IBM level sensitive scan designs (LSSD) and for the ISCAS '85 benchmark circuits [3] are reported.