Quality Factor Of Inductor Research Articles

(Invited) SOI Wafer Technology for Advanced Mos Applications

Emerging microelectronic applications such as Internet-Of-Things (IOT) or mixed signal processing utilize fully depleted MOSFETs built on SOI wafers. Advanced FD devices such as planar MOSFETs with back gate biasing require wafers with thin Si top layer as well as ultra thin BOX layer. To sustain good electrostatic control of the channel and to keep back-gate voltages reasonably low, top Si layer thickness has to be in the 5-10 nm range and BOX thickness needs to be less than 20 nm. The SmartCutTM process is the only technology that allows transferring extremely thin layers of silicon on a wide range of handling substrates with industrial quality. As threshold voltage of FD SOI transistor depends on the thickness of Si layer, the thickness has to be controlled within extremely tight tolerance, typically + /- 5A in full range of spatial frequencies spanning from 10 nm till 300 mm [1]. This creates challenge not only for manufacturing technology, but requires development of new thickness metrology. Introduction of differential reflection microscopy (DRM) [2] allows in-line SOI thickness control in wide range of spatial frequencies with unprecedented throughput and precision. The principles and main applications of DRM will be discussed in the presentation. The key process steps with their influence on specific spatial frequencies are identified. One of the main contributors to mid range frequency (in mm range) thickness variation is the interaction of propagating fracture front with acoustic waves emitted by itself. The experimental verification of this mechanism as well as the results of numerical simulations will be presented. Another critical process in SOI technology is reduction of high frequency thickness variations during finishing steps. Possibilities of using pure surface diffusion as well as chemically enhanced high temperature smoothing will be demonstrated. It will be shown that during high temperature annealing in neutral atmosphere Si surface evolution can be described by Mullings-Herring equation with two extra stochastic terms, responsible for conservative and non-conservative noise, while addition of HCl to the annealing atmosphere changes surface behavior to surface relaxation described by the Edwards-Wilkinson model. General linear 4th order surface development model is proposed covering both mechanisms. Material parameters for the model are determined experimentally in the case of HCl(<1%)/H2 etching of silicon. For some advanced applications base wafer of SOI structure can play functional role in the final device, not limited to a mechanical support. One of such examples is RF SOI substrates specifically designed for RF analog applications, such as front end RF modules in smartphones. Introduction of thermally stable layer with high density of carrier traps between BOX layer and high resistivity Si substrate significantly improves high frequency electrical parameters of the devices built on such substrates [3]. Insertion loss, second harmonic generation of coplanar waveguides as well as quality factors of inductors are such main parameters. Empirical model is presented which allows prediction of the results of RF measurements from simple SRP data.

A Widely Tunable Bandpass CMOS Filter Based on a Low-Voltage Active Inductor

A Chebyshev bandpass filter for digital TV (DTV) tuner ICs, as an RF tracking filter, based on a low-voltage tunable active inductor (TAI) is presented. The new filter has a tuning range of 200–800[Formula: see text]MHz. Independent tuning of the inductance and central frequency of the filter are very important in this wide frequency span. Adjusting the inductance for tuning of the filter should not vary its quality factor and consequently performance of the filter. Use of a feedback resistor in the active inductor makes the inductance and quality factor tuning-independent. Moreover, the feedback resistor increases the quality factor of the active inductor. Biasing the bulk terminals of the devices to a positive voltage, we achieve low threshold devices and consequently low voltage TAI. The proposed filter has IIP3 and noise figure of [Formula: see text]0.8 to 9.5[Formula: see text]dBm and 19.1 to 20.9[Formula: see text]dB, respectively. Besides, the power consumption varies from 9.6 to 25.5[Formula: see text]mW in the tuning range of 200–800[Formula: see text]MHz.

Design and analysis of a novel MEMS spiral inductor with high quality factor

In this paper a novel spiral inductor with high quality (Q)-factor is presented. Non-uniform current density distribution, especially in inner turn, increases the effective metal resistance due to skin and proximity effect. In order to overcome this problem, an improved inductor layout with non-uniform metal width and non-uniform spacing is proposed to increase the quality factor. For this inductor layout, from outer coil to inner coil, the metal widths are reduced but spacing between strips are increased. Mainly due to the decrease of eddy current loss by weakening the current crowding effect in the center of the spiral inductor. By reducing the current crowding effect, the effective resistance is minimized, thereby increase the quality factor. Simulation has been taken using COMSOL Multiphysics software. The results indicate that maximum value of quality factor and self-inductance of the novel inductor have been obtained about 80.34 and 324 nH, respectively. Which Q-factor improves 27% more than conventional inductors with uniform width. The dimension of the inductor is 1700 × 1660 μm.

(Invited) Current Status and Trends in RF Silicon-on-Insulator Material and Device

Performance of RF integrated circuit (IC) is directly linked to the analog and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic properties of the substrate. This last decade Silicon-on-Insulator (SOI) MOSFET technology has demonstrated its potentialities for high frequency commercial applications pushing the limits of CMOS technology. Partially depleted SOI MOSFET is now the mainstream technology adopted by all major foundries and fabless companies for the design of several wireless sub-systems. Today, more than 95 percent of substrates used in fabricating cellular and connectivity switches for handsets are SOI (from Navian market analyst, 2016 report) whereas it was not even in production in 2008, GaAs being mainstream at that time. Beside main switch, front-end module complexity has increased drastically: more than ten integrated switches are required in 4G Tier 1 phones, plus antenna tuners as well as Low Noise Amplifiers (LNA). RF-SOI Power Amplifiers (PA) market adoption is slowly ongoing being mainly position on entry market favoring price-performance-integration trade-off. The concept of trap-rich SOI substrate proposed in 2005 is at the origin of the RF-SOI success story. Indeed, substrate losses and crosstalk were the remaining killer features of Si-based technologies for RF applications these last decades. Thanks to the introduction of a high density of defects called traps at the buried oxide (BOX) / Si handle substrate interface, it has been possible to manufacture high-resistivity (HR) SOI substrates characterized with an effective resistivity as high as 10 kΩ.cm. Those traps originate from the grain boundaries in a thin (less than 1 µm-thick) polysilicon layer. This high-resistivity characteristic, which is conserved after a full CMOS process, translates to very low RF insertion loss (< 0.15 dB/mm at 1 GHz) along coplanar waveguide (CPW) transmission lines and purely capacitive crosstalk similarly to quartz substrate. It has been shown that the presence of a trapping layer does not alter the DC or RF behavior of SOI MOS transistors. And more importantly, it has been demonstrated that harmonics level originated from the substrate is reduced by at least 20 dB moving from standard resistivity SOI substrate (~ 10 Ω.cm) to high resistivity SOI (~ 1 kΩ.cm), and an additional drop of 40 dB is achieved with the innovative trap-rich HR SOI substrate. The low harmonic level achieved is comparable with insulating substrate. The improvement of the HR SOI substrate with the introduction of defects brings also clear benefits for the integration of passives, such as the quality factor of spiral inductors, tunable MEMS (microelectromechanical systems) capacitors, as well as for the reduction of the substrate noise (crosstalk) between devices integrated on the same chip, etc. Université catholique de Louvain and Soitec have been working together to manufacture the trap-rich SOI substrate concept to further improve the high-frequency performance of commercially available HR-SOI substrates. In 2013, Soitec has unveiled a new flavor of HR-SOI called RF-eSITM-SOI, for enhanced Signal IntegrityTM substrate with a measured effective resistivity as high as 10 kΩ.cm. RF-eSI-SOI substrate can really be considered as a lossless Si-based substrate. Beyond switch, RF-eSI-SOI technology opens the path to further system integration in the Front-End Module (FEM) space as well as even more complex mixed signal System-on-Chip. Based on its 45 nm baseline SOI process, GlobalFoundries just released a RF-SOI mmW offering targeting applications like 5G, satellite communication, automotive radar, WiGig, backhaul. The SOI substrates roadmap for RF and millimeter-waves applications will be presented. Future generations of mobile communication systems such as 5G or the Internet-of-Things will require transistors with better high frequency performance at lower power consumption. The advanced MOS transistors in competition are FinFET and Ultra Thin Body and Buried oxide (UTBB) SOI MOSFETs. Both devices have been intensively studied these last years. Most of the reported data concern their digital performance. Their analog/RF behavior will be described and compared in the paper. Both show pretty similar characteristics in terms of transconductance, Early voltage, voltage gain, self-heating issue but UTBB outperforms FinFET in terms of cutoff frequencies thanks to their relatively lower fringing parasitic capacitances. The relative impact of the transistor characteristics and the substrate properties on different RF ICs performances will be presented. As it will be demonstrated, the use of specific RF test structures at the early stage of a technological node development is of first importance to analyze the transistor parasitic resistances and capacitances, the transistor cutoff frequencies, the self-heating, and the substrate coupling and non-linear behavior.

Phase noise reduction in LC cross coupled oscillators using sinusoidal tail current shaping technique

In this paper, using the concept of impulse sensitivity function (ISF) in Hajimiri's phase noise model, a novel circuit method for phase noise reduction in LC cross coupled oscillators is proposed. Based on the proposed technique, at outputs zero crossing points, where ISF is maximum, current supplying to the transistor pair is stopped by two added transistors. Due to the shaped effective ISF waveform and also reduction of its RMS value, phase noise is decreased. In addition, the cascode structure of the proposed technique leads to more phase noise reduction due to the suppression of the transistors noise power. The proposed circuit is designed for 10 GHz output frequency and inductor quality factor of 12, and simulated in a standard 0.18 µm CMOS technology with a 1.8 V supply. Compared to the simple cross coupled oscillator, phase noise at 1 MHz and power consumption are reduced by 8 dB and 26%, respectively. The phase noise and FOM for the proposed oscillator at 1 MHz offset frequency are ýý107.8 dBc/Hz and 186.2 dB, respectively.

Study of variability performance of CMOS active inductors

The development of CMOS technology has led to the integration of communication circuits on a single chip. Inductors constitute an essential part of a RF front ends. Employment of spiral inductors has put several limitations on such RF circuits. Spiral inductors are fixed, bulky, cover large area and can’t be scaled with the process technologies. Also, due to the resistive losses and substrate losses, the quality factor is limited. An alternate way to emulate inductor behavior is using active inductors. Active inductors are area-efficient, support tunable inductance, quality factor, self-resonant frequency and can be scaled with process technologies. However, the active inductors are too sensitive to process, supply voltage and temperature variations. In this paper, four active inductor architectures i.e. basic, resistive feedback, Weng-Kuo and regulated cascode active inductor are designed. The quality factor performance of the four active inductor circuits is evaluated. Further, to demonstrate the performance of active inductors, bandpass filter configurations are implemented. The impact of process, voltage and temperature variations on the quality factor of active inductors and resonant frequency of bandpass filters is studied. Simulations are carried out at 180-nm technology node.

3D IPD on Thru Glass Via Substrate using panel Manufacturing Technology

Abstract As electronic products become smaller and thinner with increasing number of functions, the demand for high density and high integration becomes stronger. Glass has many properties that make it an ideal substrate for high integration substrate such as; ultra high resistivity, adjustable thermal expansion (CTE) high modulus, low dielectric constant, low dielectric loss and manufacturability with large panel sizes. Multi-bands with carrier aggregation, Wi-Fi/GPS coexistence, and LTE-U make RF front end more and more complicated. 3D IPD (integrated passive devices) on Glass substrate technology could be advantage solution include reducing power consumption and small form factor. This paper presents a demonstration of 3D RF front end filters using 3D solenoid inductors with through glass vias (TGV) and Cu-SiN-Cu MIM structure on Gen1 glass substrate (300mm × 400mm) panel format using color filter manufacturing line for flat panel display. For inductors, drastic performance (size and low resistance therefore high-quality factor) improvement have been demonstrated by technology evolutions from 3D solenoid using TGV with conformal Cu plating method, achieving low resistance of 3.1mohm per 70um diameter TGV on a 400um thick glass panel. This low-resistance TGV with 2.7mOhm/sq TGV connections on both sides of the glass substrate, record high inductor quality factor of 39 was obtained at 2.5GHz using five and half turn inductor of 7.9nH inductance, For capacitors, we have successfully integrated a Cu MIM (metal-insulator-metal) structure by using 15um thick Cu plates and dielectric, resulting in high capacitance density of 0.26nF/mm2 for RF application. By integrating TGV inductor-first and MIM capacitor-next, high-performance and high-density LC components are synthesized to perform as RF front end filters such as low-pass filters, diplexers, triplexers, and multiplexers. The 3D inductors, Cu MIM, LC resonators and filters were successfully integrated using glass panel manufacturing infrastructure for the first time. Process characterization and process control monitors were evaluated at the panel level to address high-volume and high-yield manufacturability of RF filters with the unprecedented filter performance in terms of insertion loss and out of band rejections in smaller form factor than any other technologies have achieved so far. Furthermore, the TGV filters were mounted on electrical evaluation boards as well as JEDEC standard testing boards to check any device-level, chip-level, and board-level reliabilities associated with glass or TGV materials as well as their interaction with Cu, SiN, polymer inter layer dielectric materials, and solder joints, showing no performance degradations during thermal cycling, drop shock, bending, or high-power testing situations.

Ultra-low-loss high-pass filter with air-core short-circuit coaxial cable

This paper presents a novel ultra-low-loss high-pass filter with 3 dB cutoff frequency of 890 MHz for astronomical receiver radio frequency interference mitigation application. The filter consists of three series capacitors, four shunt inductors, and microstrip circuit board. Specially, 4 shunt inductors are actualized by fabricating air-core short-circuit coaxial cable inductors in the filter box body, and the quality factor of these cable inductors is up to 762.2 and 1046, respectively, at 1.4 GHz. In the expected passband of 1.1–1.9 GHz, S parameters measurement show that insertion loss is lower than 0.16 dB and two-port return loss is larger than 20 dB; noise measurement show that filter noise temperature is lower than 8 at 300 K ambient temperature. Noise sources of this filter are analyzed by simulation and measurement.

Quality factor enhancement of an on-chip inductor through the slot-trace method

This study investigated a slot-trace method to enhance the quality factor of an on-chip inductor. To verify the effect of a slot-trace method with lowered trace loss, and to compare it with a method lowering the substrate loss, three on-chip inductors were implemented with a 0.35 μm COMS–MEMS process: a CMOS inductor, a COMS–MEMS inductor, and a COMS–MEMS inductor with a slot trace. The results show that the substrate loss mainly lowers the quality factor performance at frequencies above 2 GHz. Unlike substrate loss, trace loss influences the quality factor from low to high frequencies, and the trace loss should not be ignored. Moreover, the results show that the slot-trace method can improve the quality factor, making it useful in on-chip inductor design for the circuits of wireless communication system applications.

60 GHz-Band Low-Noise Amplifier

This paper presents the design of a 60[Formula: see text]GHz-band LNA intended for the 63.72–65.88[Formula: see text]GHz frequency range (channel-4 of the 60[Formula: see text]GHz band). The LNA is designed in a 65-nm CMOS technology and the design methodology is based on a constant-current-density biasing scheme. Prior to designing the LNA, a detailed investigation into the transistor and passives performances at millimeter-wave (MMW) frequencies is carried out. It is shown that biasing the transistors for an optimum noise figure performance does not degrade their power gain significantly. Furthermore, three potential inductive transmission line candidates, based on coplanar waveguide (CPW) and microstrip line (MSL) structures, have been considered to realize the MMW interconnects. Electromagnetic (EM) simulations have been performed to design and compare the performances of these inductive lines. It is shown that the inductive quality factor of a CPW-based inductive transmission line ([Formula: see text] is more than 3.4 times higher than its MSL counterpart @ 65[Formula: see text]GHz. A CPW structure, with an optimized ground-equalizing metal strip density to achieve the highest inductive quality factor, is therefore a preferred choice for the design of MMW interconnects, compared to an MSL. The LNA achieves a measured forward gain of [Formula: see text][Formula: see text]dB with good input and output impedance matching of better than [Formula: see text][Formula: see text]dB in the desired frequency range. Covering a chip area of 1256[Formula: see text][Formula: see text]m[Formula: see text]m including the pads, the LNA dissipates a power of only 16.2[Formula: see text]mW.

60 GHz 5‐bit digital controlled phase shifter in a digital 40 nm CMOS technology without ultra‐thick metals

A 5-bit digital controlled switch-type passive phase shifter realised in a 40 nm digital CMOS technology without ultra-thick metals for the 60 GHz Industrial, Scientific and Medical (ISM) band is presented. A patterned shielding with electromagnetic bandgap structure and a stacked metals method to increase the on-chip inductor quality factor are proposed. To reduce the insertion loss from the transistors, the transistor switches are implemented with a body-source connection. For all 32 states, the minimum phase error is 1.5°, and the maximum phase error is 6.8°. The measured insertion loss is -20.9 ± 1 dB including pad loss at 60 GHz and the return loss is >10 dB over 57-64 GHz. The total chip size is 0.24 mm2 with 0 mW DC power consumption.

Optimal design of a wireless power transfer link using parallel and series resonators

The optimal design problem for a wireless power transfer link based on a resonant inductive coupling is addressed in this paper. It is assumed that the magnetic coupling coefficient and the inductor quality factors are known. By employing the conjugate image impedances, the values of the inductances realizing the optimal design with respect to given values of the network input and load impedances are derived. It is demonstrated that there is just one optimal design maximizing both the power delivered to the load and the power transfer efficiency of the link. The four possible schemes corresponding to the use of a parallel or a series arrangement for the two coupled resonators (Parallel-Parallel, Series-Series, Parallel-Series, and Series-Parallel) are considered and discussed. Closed form analytical formulas are derived and validated by circuital simulations.

Comparison of the effects of 60 nm and 96 nm thick patterned permalloy thin films on the performance of on-chip spiral inductors

In our earlier work it was shown that the 60nm domain patterned Permalloy, incorporated on on-chip spiral inductors, gave better performance at frequencies greater than 5GHz compared to the bulk Permalloy incorporated inductors, and the control structure. In this paper we compare the effects of 60nm and 96nm thick domain patterned Permalloy thin films, on the performance of on-chip spiral inductors. Experimental results show that the 60nm thick both bulk and patterned Permalloys provide more improvement in inductance and quality factor of inductors, compared to that of 96nm.

OPTIMIZATION OFSPIRAL INDUCTOR WITH DIFFERENT INNER DIAMETERS

A scalable and highly accurate RF/Microwave symmetricalinductor has been designed using microstrip line. The 18 circular and 18 square structures are optimized with 600MHz operating frequency. The characteristic interest on high frequency operating circuits is inductance value and quality factor of the spiral inductor. The value of the spiral inductor is depends on conductor width (W) space between the conductor (S), turns (n) outer diameter and inner diameter of the spiral inductor. In this design change the distribution of an inner diameter from 5mil to 10milfor 3 to 5 turns of spiral inductors. The optimization of inner diameter distribution is done by keeping space (1mil)between the conductor and width (2mil) of the conductor as constant. The changing inner diameter will effect to change in magnitude of the inductance and quality factor due passive capacitive and inductive reactance effect. These spiral inductors are designed using aluminum (Al) substrate material with 15mil height from the ground plane. The cupper material is used as a conductor of thickness 0.302mm. The aim of this paper is to compare the electromagnetic simulated results with simple equations of modified wheeler (MW), current sheet Approximation (CSA) and monomial equation (ME). The passive component effect the spiral inductor is examines the variation of inductance and quality factor. The observed electromagnetic field simulated results gives better agreement with standard simple mentioned equations with 600MHz operating frequency. The validation of spiral inductor is done with different inner diameter (5mil to 10mil) and number of turns (3turns to 5 turns) of the spiral inductor.

Optimization of on-chip spiral inductors using coupled NN and TLBO algorithms for low-loss lumped-element CMOS power dividers

An efficient layout-level optimization technique based on NN+TLBO algorithm is presented to maximize the quality factor of on-chip spiral inductors at a given frequency. A multi-layer artificial neural network (ANN) is developed to model the on-chip inductors. TLBO algorithm is used in order to optimize the layout space for the on-chip spiral inductors considering constraints of design specifications and desired accuracy level. A four-way K-band lumped-element power divider (PD) is designed in 0.18m CMOS technology to validate the characterized spiral inductor. The PD achieves an insertion loss less than 2.1 dB, an input return loss better than 10 dB, an output return loss less than 12 dB, and a port-to-port isolation higher than 14 dB from 18 to 26 GHz (K-Band). The chip area is about 0.415 mm 2 including bonding pads.

Design considerations on wideband envelope termination for high efficiency RF power amplifiers

Design approach of wideband envelope termination (ET) for high efficiency RF power amplifiers (PAs) is discussed, considering power loss subject to design constraints including envelope bandwidth, inductor quality factor, and transistor output impedance. Analysis shows that the optimum ET topology depends on the design constraints. For LTE-advanced transmission with 80 MHz channel bandwidth, a novel wideband ET is designed using an AC-terminated third-order LC filter (LCF-ET), providing 3 dB envelope impedance bandwidth of 150 MHz. Measured results demonstrate 1.75 dB envelope power loss and −39.2 dB normalised root-mean-square error with the LTE envelope signals. For the LTE signal with 10.3 dB peak-to-average power ratio, the average power efficiency of an ideal Class-A RF PA with the LCF-ET prototype is calculated as 33.4% from the measured 1.75 dB envelope power loss, which exceeds 4.7% and 24.0% average power efficiency of conventional Class-A and Class-B PAs without ET.

On the Efficacy of Through-Silicon-Via Inductors

Through-silicon-vias (TSVs) can potentially be used to implement inductors in 3-D integrated systems for minimal footprint and large inductance. However, different from conventional 2-D spiral inductors, TSV inductors are fully buried in the lossy substrate, thus suffering from low quality factors. In this paper, we systematically examine how various process and design parameters affect their performance. A few interesting phenomena that are unique to TSV inductors are observed. We then propose a novel shield mechanism utilizing the microchannel, a technique conventionally used for heat removal, to reduce the substrate loss. The technique increases the quality factor and inductance of the TSV inductor by up to 21× and 17×, respectively. Finally, since full-wave simulations of 3-D structures are time-consuming, we develop a set of compressed sensing-based design strategies for microchannel-shielded TSV inductors, which only requires a minimal number of simulations. It enables us to implement microchannel-shielded TSV inductors of up to 5.44× reduced area compared with spiral inductors of the same design specs (quality factor, inductance, and frequency). To the best of our knowledge, this is the very first in-depth study on TSV inductors to make them practical for high-frequency applications. We hope our study shall point out a new and exciting research direction for 3-D integrated circuit designers.

Improvement in inductance and Q-factor by laser microstructuring of ferromagnetic on-chip thin film inductors

In this work, we examine the potential improvement in inductance (L) and quality factor (Q) of on-chip ferromagnetic thin film inductors through the formation of conical microstructures by localized ultraviolet laser irradiation on ferromagnetic thin film. Parameters affecting L and Q, and arising from the surface modification upon laser irradiation include thickness of the film, size, and density of the structures. The thickness of the film is optimized to 0.2 μm, and at least 18% increase in inductance and 25% increase in Q-factor for NiFe thin film in comparison to the conventional spiral inductor is expected. L and Q values of NiFe films with and without microstructuring are compared, and a 7% increase is predicted for the microstrucired film. The proposed fabrication process, including the laser microstructuring technique, is likely to provide a significant flexibility, cost effectiveness and even better parameters, if other material systems are considered.

Improved-Q inductors using airbridges for GaN phase shifters

This article proposes the use of inductors suspended in air to increase the self-resonance frequency and quality factor of inductors used in high-frequency lumped MMIC designs. This technique is compatible with MMIC processes having airbridges with no additional processing, which are quite common in III–V technologies. A measured example demonstrates lower dispersion, an increase in quality factor of 18% and a 4% increase in the self-resonance frequency of a 1 nH inductor in a GaN MMIC process with a 1 μm airbridge. As a further demonstration, the technique is applied in the design of a high-power 0°/45° switched phase shifter designed around 25 GHz. This phase shifter MMIC uses GaN HEMTs which have a peak ft of 27 GHz and offers wideband performance. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:1455–1459, 2015

Silicon-Embedded RF Micro-Inductors for Ultra-Compact RF Subsystems

Advances in 2.5D and 3D integration technologies are enabling ultra-compact multi-chip modules. In this abstract, we present the design, fabrication, and experimental characterization of RF inductors microfabricated inside deep silicon recesses. Because silicon is often used as a substrate of packaging material for 3D integration and microelectromechanical systems (MEMS), developing microfabrication technologies to embed passive components in the unused volume of the silicon package is a promising approach to realize ultra-compact RF subsystems. Inductors and capacitors are critical in dc-bias circuits for MMICs in order to suppress low-frequency oscillations. Because it is particularly important to have these passive components as close to the MMIC as possible with minimum interconnection parasitics, silicon-embedded passives are an attractive solution. Further, silicon-embedded passives can potentially reduce the overall volume of RF subsystems when compared to modules using discrete passives. Although inductors inside the volume of silicon wafers have previously been reported, they typically operated in the 1–200 MHz frequency range, mostly featuring inductors with wide (50–100 μm) conductors and wide (50–100 μm) interconductor gaps due to fabrication limitations. We first explored process limitations to fabricate structural and electrical features inside 75 to 100-μm-deep silicon cavities. The cavities were etched into the silicon using deep reactive ion etching. Inside these recesses, we demonstrated the fabrication of thin (0.2 μm) and thick (5 μm) gold patterns with 3 μm resolution using lift-off and electroplating processes, respectively. The lift-off process used an image reversal technique, and the plated gold conductors were fabricated through a 6.5-μm-thick photoresist mold. The feature sizes ranged from 3 to 50 μm. For photoresist exposure, an i-line Canon stepper was utilized, and configured specifically to focus at the bottom of the cavities, a key process requirement to achieve high-resolution features. These microfabrication results enabled the design of high-performance RF inductors, which will be discussed in the next section. In addition, we demonstrated the fabrication of 30-μm-deep 3-μm-diameter silicon-etched features inside these cavities, a stepping stone towards achieving high-capacitance-density integrated trench capacitors embedded inside silicon cavities. The silicon-embedded RF inductors were microfabricated on 500-μm-thick high-resistivity (ρ &amp;gt; 20,000 Ω.cm) silicon wafers. First, 75-μm-deep cavities were etched using DRIE. Various two-port coplanar waveguide (CPW) inductor designs were microfabricated. The inductor microfabrication relied on sputtered titanium/gold seed layers, thick AZ4620 photoresist molds, and three 5-μm-thick electroplated gold layers stacked on top of each other to define the inductor conductor and connections. By using a combination of three electroplated layers, high-power-handling low-loss inductors were fabricated. Measurements were performed on a RF probe station, with on-wafer calibration structures. The losses associated with the CPW launchers were de-embedded prior to inductor measurements, and inductor quality factor greater than 40 was measured on various inductors with inductance of approximately 1 nH, and self-resonant frequency at 30 GHz. These results were in agreement with models performed using SONNET simulation package, and are comparable with than that of inductors fabricated on planar silicon wafers.