Inductor Current Ripple Research Articles

New hysteresis‐current‐controlled buck converter with AC sensing techniques

A new hysteresis-current-controlled buck converter with alternating current (AC) sensing techniques is presented in this Letter. The proposed AC sensing technique senses the inductor current ripple by sensing the voltage at two terminals of the inductor. Accompanying with hysteresis-current-controlled technique and a type-III compensator, the transient response can be accelerated. The simulation result shows the response time is 0.7 µs when the load current switch from 150 to 600 mA and the maximum efficiency is 94.6%.

Analysis, Design and Control of an Integrated Three-Level Buck Converter under DCM Operation

A three-level buck (TLB) converter has the characteristics of higher voltage conversion efficiency, lower inductor current ripples, output voltage ripples and voltage stresses on switches when compared with the buck converters in continuous conduction mode (CCM). With a TLB converter integrated on a chip, we cannot avoid its discontinuous conduction mode (DCM) operation due to a smaller inductance and load variation. In this paper, we’ll present and discuss the analysis, design and control of a TLB converter under DCM operation, implemented in a 65[Formula: see text]nm CMOS process. Transistor level simulation results show that when the TLB converter operates at 100[Formula: see text]MHz with a 5[Formula: see text]nH on-chip inductor, a 10[Formula: see text]nF output capacitor and a 10[Formula: see text]nF flying capacitor, it can achieve an output conversion range of 0.7–1.2[Formula: see text]V from a 2.4[Formula: see text]V input supply, with a peak efficiency of 81.5%@120[Formula: see text]mW. The output load transient response is 100[Formula: see text]mV with 101[Formula: see text]ns for undershoot, and 86[Formula: see text]mV with 110[Formula: see text]ns for overshoot when [Formula: see text]–100[Formula: see text]mA. The maximum output voltage ripple is less than 19[Formula: see text]mV.

4-level capacitor-clamped boost converter with hard-switching and soft-switching implementations

This paper presents parameters analysis of 4-level capacitor-clamped boost converter with hard-switching and soft-switching implementation. Principally, by considering the selected circuit structure of the 4-level capacitor-clamped boost converter and appropriate pulse width modulation (PWM) switching strategy, the overall converter volume able to be reduced. Specifically, phase-shifted of 120° of each switching signal is applied in the 4-level capacitor-clamped boost converter in order to increase the inductor current ripple frequency, thus the charging and discharging times of the inductor is reduced. Besides, volume of converters is greatly reduced if very high switching frequency is considered. However, it causes increasing of semiconductor losses and consequently the converter efficiency is affected. The results show that the efficiency of 2-level conventional boost converter and 4-level capacitor-clamped boost converter are 98.59% and 97.67%, respectively in hard-switching technique, and 99.31% and 98.15%, respectively in soft-switching technique. Therefore, by applying soft-switching technique, switching loss of the semiconductor devices is greatly minimized although high switching frequency is applied. In this study, passive lossless snubber circuit is selected for the soft-switching implementation in the 4-level capacitor-clamped boost converter. Based on the simulation results, the switching loss is approximately eliminated by applying soft-switching technique compared to the hard-switching technique implementation.

A Cross-Regulated Closed-Loop Control for Hybrid L-Z Source Inverter

Recently, switched inductor-impedance source inverter (L-ZSI) based hybrid converter was reported as a potential candidate for the dual output (dc and ac) applications. This converter has two operating modes based on inductor current nature: 1) continuous current mode (CCM); and 2) discontinuous current mode (DCM). However, the converter performs well only during CCM. To get rid of problems present in hybrid L-ZSI, modified hybrid L-ZSI (MHLZSI) was reported. To demarcate the CCM and DCM, boundary condition was derived based on the average inductor current. However, the actual boundary condition is dependent on the combined effect of inductor current ripple and average inductor current. In this paper, theoretical analysis is presented by taking into account the effect of inductor current ripple. Furthermore, it is proved that MHLZSI is capable of achieving higher gain when operated in DCM. In addition, a closed-loop control for MHLZSI is designed. State space analysis is presented to derive the output to control transfer function for both dc and ac loads. Both the controllers are designed based on PI control to ensure cross regulation. Theoretical analysis is validated by experimental analysis.

Double-Ended Active-Clamp Forward Converter With Low DC Offset Current of Transformer

The double-ended (DE) active-clamp forward (ACF) converter is one of the attractive dc-dc converters for the power supply of digital devices due to a simple structure and zero voltage switching (ZVS) capability of primary switches. However, due to a dc offset current of transformer, the size and core loss of transformer are increased. In this paper, a new DE-ACF converter having an additional switch and a diode is proposed to achieve a low dc offset current of transformer by charging a clamp capacitor additionally during a turn-off interval between main switches. Thus, the transformer size can be reduced in the proposed converter. Furthermore, since the output inductor current ripple is reduced, the primary and secondary conduction losses can be decreased under medium and heavy loads. As a result, the proposed converter can have higher efficiency than conventional DE-ACF converter. The validity of the proposed converter is confirmed by experimental results from a prototype with 400 V nominal input voltage and 400 W (12 V/33.33 A) output.

A Family of PWM Control Strategies for Single-Phase Quasi-Switched-Boost Inverter

This paper proposed a novel family of pulsewidth modulation (PWM) strategies for single-phase quasi-switched boost inverter (qSBI). By combining shoot-through (ST) mode in the inverter's switches and the turning- on state of an additional switch, the qSBI produced a high voltage gain without adding any passive components. Compared to the conventional PWM strategy for the same input and output voltage gain, the introduced PWM strategies for qSBI could reduce voltage stress across semiconductors and capacitor with the following additional merits: having smaller high-frequency inductor current and capacitor voltage ripples, using high modulation index with low ST duty cycle, and having higher efficiency. Circuit analysis, operating theories, and simulation results of the single-phase qSBI with the introduced PWM5 strategy are shown. A 500-W laboratory prototype was constructed and the effectiveness of the introduced PWM strategy was validated. The qSBI with the proposed PWM strategies is suitable for applications where the required voltage gain lies between 2 and 3.

Nonisolated High Step-Down Converter With ZVS and Low Current Ripples

In this paper, a nonisolated high step-down converter is proposed. Energy transfer capacitor and built-in transformer are employed to achieve a very high step-down conversion ratio. Due to the interleaved technique, small values of output inductance can be used, leading to a fast transient response. Furthermore, the use of a coupled inductor reduces inductor current ripples, which implies lower losses. Two main switches and two synchronous rectifiers are used in the converter and all can achieve zero-voltage-switching. As no floating switches are employed, grounded gate drivers and boost strap drivers can be used, avoiding the use of complex isolated gate drivers. In addition, if the switches are shorted, the high input voltage does not appear at the output; thus, the load is protected. A 48 V/1 V 30 A prototype was built, and experimental results are provided to verify the performance of the converter.

Optimized Design of the Neutral Inductor and Filter Inductors in Three-Phase Four-Wire Inverter With Split DC-Link Capacitors

The three-phase four-wire inverter with split dc-link capacitors can supply unbalanced loads. For the purpose of reducing the filter inductors, a neutral inductor could be introduced into the neutral line. This paper analyzes the operation principle of the three-phase four-wire inverter with split dc-link capacitors when a neutral inductor is introduced. It is illustrated that the neutral inductor can reduce the zero-sequence switching harmonics in the voltages between the phase-leg midpoints and the output neutral point, thus the filter inductors can be reduced. The optimized design of the neutral inductor and filter inductors is proposed with the considerations of the inductor current ripple, the ability of supplying unbalanced loads, and the total energy stored in the inductors. The equivalent circuits of the three-phase four-wire inverter with split dc-link capacitors and neutral inductor is derived in the α-β-0 frame, and the zero-axis voltage regulator is modified to suppress the third-order harmonic in the zero-sequence current caused by the deadtime of the drive signals for the power switches. Finally, the experimental results from a 9-kW prototype are provided to prove the effectiveness of the proposed optimized design of the neutral inductor and filter inductors and the control strategy of the inverter.

A CMOS PFM buck converter employing a digitally programmable voltage level-shifting technique

This paper describes a CMOS pulse frequency modulation (PFM) buck converter employing a digitally programmable voltage level-shifting technique capable of adjusting peak inductor current and output ripple voltage for different load currents. The conventional PFM buck converters employ either an adaptive delay time control circuit or a fixed delay time control circuit to control output ripple voltage and power efficiency with the switching frequency. However, they suffer from a large peak inductor current, resulting in reduced power efficiency. The digitally programmable voltage level-shifting circuit, based on a common source amplifier, is capable of sensing inductor current through the voltage drop caused by on-resistance of the power switch, and can control peak inductor current. The precision needed to control the magnitude of the peak inductor current can be obtained with the number of bits in the digitally programmable voltage level-shifting circuit that are dependent on the input common mode range of the comparator. Employment of one comparator with pre-control logic and post-control logic circuits allows the proposed circuit to improve power efficiency by removing additional circuits, compared with the conventional PFM buck converters. The proposed converter was implemented with a 180 nm CMOS process. The effective chip size of the core block occupies 900μm × 590μm. The proposed PFM mode buck converter with a precision of four bits to control peak inductor current is capable of accommodating an input voltage range of 2.7–3.3 V, and can produce output voltage of 1.2 V. The operational switching frequency measured is on the order of several to several hundred kHz, the load current range is under 150 mA, and the measured output ripple voltage varied, depending on the digital programming status. The measured power efficiency ranged between 70 and 84%.

Switching frequency control method based on short prediction horizon control algorithm of Quasi-Z source inverter

In order to overcome the problem of large inductance current ripple and poor output current quality caused by lower switching frequency in model predictive control (MPC). A short prediction horizon control algorithm is proposed, and the relationship between the prediction horizon and the switching frequency is analyzed, which also considered the influence of the switching frequency of the inverter. In the proposed algorithm the optimal vector is selected based on the historical switching state. Finally the proposed method can effectively reduce the inductor current ripple and improve the output current quality of the inverter, which is proved by simulation and experiment.

An improved integrated control modeling of a high-power density interleaved non-inverting buck-boost DC-DC converter

PurposeThis paper aims to propose a novel integrated control method (ICM) for high-power-density non-inverting interleaved buck-boost DC-DC converter. To achieve high power conversion by conventional single phase DC-DC converter, inductor value must be increased. This converter is not suitable for industrial and high-power applications as large inductor value will increase the inductor current ripple. Thus, two-phase non-inverting interleaved buck-boost DC-DC converter is proposed.Design/methodology/approachThe proposed ICM approach is based on the theory of integrated dynamic modeling of continuous conduction mode (CCM), discontinuous conduction mode and synchronizing parallel operation mode. In addition, it involves the output voltage controller with inner current loop (inductor current controller) to make a fair balancing between two stages. To ensure fast transient performance, proposed digital ICM is implemented based on a TMS320F28335 digital signal microprocessor.FindingsThe results verify the effectiveness of the proposed ICM algorithm to achieve high voltage regulating (under 0.01 per cent), very low inductor current ripple (for boost is 1.96 per cent, for buck is 1.1) and fair input current balance between two stages (unbalancing current less than 0.5A).Originality/valueThe proposed new ICM design procedure is developed satisfactorily to ensure fast transient response even under high load variation and the solving R right-half-plane HP zeros of the CCM. In addition, the proposed method can equally divide the input current of stages and stable different parallel operation modes with large input voltage variations.

A Spur-Reduction DC–DC Converter With Active Ripple Cancelation Technique

This paper presents an active ripple cancelation (ARC) technique for reducing the switching harmonics of the output voltage of a dc–dc converter. An ARC module injects an ac current to accurately cancel the inductor current ripple while the switching converter provides the dc output current. As a result, the output spur of the switching converter can be reduced effectively. However, due to the ARC module, the proposed power converter includes two complex poles. To ensure the system stability and achieve accurate ripple cancelation, a proposed control method and an adaptive phase-lock circuit are utilized. Furthermore, the ripple cancelation capability is independent of duty cycle, load current, and other converter parameters. The measurement results demonstrate that the switching spur reduction with ARC technique can achieve 28 dB while the noise floor is kept the same.

A Self-Oscillating Boosting Amplifier With Adaptive Soft Switching Control for Piezoelectric Transducers

This paper describes the design of a high-voltage amplifier for a piezoelectric transducer used in underwater communication applications, which incorporates boosting and signal generation within a single boost converter stage improving the total efficiency of the system. The proposed architecture combines hysteretic ripple current-mode control with an adaptive soft switching technique to achieve improved power efficiency over the full output power range. This is achieved by dynamically controlling the inductor current ripple to keep the converter running in soft switching. The feedback control and the soft switching regulation are implemented in a 0.25 $\mu \text{m}$ 60-V TSMC process with an external power stage. The system achieves a peak efficiency of 85% at 20 W of output power up to 30-kHz signal frequency.

Sensorless predictive current control with a charge balance current estimator for boost converters based on discrete‐time model considering current ripple

The performance of a sensorless predictive current controlled boost converter is usually susceptible to the accuracy of the employed converter and current estimator models. Since the accuracy of conventional current estimator would be degraded due to parasitic parameter variations, a charge balance current estimator (CBCE) is proposed to overcome this issue. Its estimation of peak inductor current is based on the charge balance principle of output capacitor and characteristics of inductor current ripple. Only one parasitic parameter - capacitor equivalent series resistance (ESR) is used in CBCE. Furthermore, the capacitor ESR is also estimated together with output load by a proposed equivalent load estimation scheme which can improve the current estimation accuracy. Besides, to achieve a high dynamic performance digital control, a discrete-time model considering current ripple is developed, in which the ripple is taken into account rather than treats inductor current as a constant in each switching cycle. It can achieve a higher accuracy than conventional averaged model, especially in the high-frequency region. Finally, its effectiveness is verified by simulation and experiment results.

Low‐power non‐ideal pulse‐width modulated DC–DC buck–boost converter: design, analysis and experimentation

In this study, parasitic elements (non-idealities) effect on a low-power DC-DC buck-boost converter design is analysed and investigation is carried out by both large (i.e. steady-state) and small signal analysis. The large signal analysis of non-ideal buck-boost converter explored the significant information such as nearly accurate duty cycle, maximum allowable duty cycle and maximum possible output voltage. Further, accurate mathematical design formulae are derived of inductor and capacitor for specified inductor current ripple and output voltage ripple (OVR), respectively. Moreover, consequences of different equivalent series resistance of capacitor on OVR is examined. Subsequently, the exact model of buck-boost converter is procured from the small signal analysis, which is almost analogous to practical system. In order to show the impact of non-idealities on controller design, an internal model control PID controller is designed for ideal, semi-non-ideal and complete non-ideal systems based on their respective models, which shows the controller based on non-ideal model provides very close results to practical system. Conclusively, the complete theoretical explorations are justified by simulations and substantiated by experimental results.

Three-Level Quasi-Switched Boost T-Type Inverter: Analysis, PWM Control, and Verification

In this paper, a three-level quasi-switched boost T-type inverter (3L qSBT <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> I) is proposed. A new pulse-width modulated (PWM) control method is presented to reduce the inductor current ripple of the qSBT <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> I. In the introduced PWM technique, the shoot-through duty cycle is maintained constant to keep the modulation index as high as possible. Then, the only control parameters of the qSBT <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> I are the duty cycles of the two additional switches. By controlling the duty cycles of the two additional switches, the voltage gain of the proposed qSBT <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> I can be improved to a value larger than that of the conventional 3L impedance source inverters. The steady-state analysis, operating principles, and comparisons with the impedance source-based 3L inverters are presented. A 1-kW prototype is constructed to verify the operating principle of the 3L qSBT <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> I. An indirect dc-link voltage regulator and a capacitor voltage-balance controller are applied to the proposed qSBT <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> I. Simulation and experimental results are presented.

Model-Based Current Control for Single-Phase Grid-Tied Quasi-Z-Source Inverters With Virtual Time Constant

In this paper, a model-based current control (MBCC) approach with a compensating of dc-side inductor current ripple, active damping, and virtual time constant is proposed for single-phase grid-tied quasi-Z-source inverters with an LCL filter. The idea behind the ripple compensation is based on the inherent relationship between the ripple components of the dc-side inductor and capacitor voltages. It is shown that dc-side inductor current ripple can be compensated if the conventional simple boost control involving proportional-integral (PI) controllers is modified by subtracting the measured dc-side inductor voltage from the error signal of the first PI controller. Also, it is shown that the proposed MBCC causes the ac-side inverter current to track its reference in all circumstances. In addition, a virtual time constant is added to the control variable so that the dynamics of the ac-side inverter current can be adjusted as desired. Finally, in order to damp the LCL resonance, an active damping method is employed in the closed-loop system by modifying the ac-side reference inverter current. Experimental results are presented to show the validity and performance of the proposed control approach.

Predictive Current Control of Boost Three-Level and T-Type Inverters Cascaded in Wind Power Generation Systems

A topology structure based on boost three-level converters (BTL converters) and T-type three-level inverters for a direct-drive wind turbine in a wind power generation system is proposed. In this structure, the generator-side control can be realized by the boost-TL converter. Compared with the conventional boost converter, the boost-TL converter has a low inductor current ripple, which reduces the torque ripple of the generator, increases the converter’s capacity, and minimizes switching losses. The boost-TL converter can boost the DC output from the rectifier at low speeds. The principles of the boost-TL converter and the T-type three-level inverter are separately introduced. Based on the cascaded structure of the proposed BTL converter and three-level inverter, a model predictive current control (MPCC) method is adopted, and the optimization of the MPCC is presented. The prediction model is derived, and the simulation and experimental research are carried out. The results show that the algorithm based on the proposed cascaded structure is feasible and superior.

PWM Control Scheme For Quasi-Switched-Boost Inverter to Improve Modulation Index

The simple boost control (SBC) method is usually used to control the shoot-through state in a single-phase single-stage quasi-switched boost inverter (qSBI). This paper proposes a new pulse-width modulation (PWM) control scheme to improve the modulation index for the qSBI. The advantages of the proposed method for the qSBI over the conventional SBC method are as follows: 1) the modulation index is larger; 2) the voltage stress on the capacitor, diodes, and switches is reduced significantly; 3) the high-frequency peak-to-peak inductor current and capacitor voltage ripples are smaller; 4) the shoot-through current is lower; and 5) the efficiency is higher. The operating principles and circuit analysis for the proposed PWM control scheme are shown. To verify the performance of the proposed PWM control method, a 400W prototype was built with a 110 V/50 Hz output voltage. The experimental results matched those of the theoretical analysis.

Selection of Coupling Factor for Minimum Inductor Current Ripple in Multi-winding Coupled Inductor Used in Bidirectional DC-DC Converters

Selection of Coupling Factor for Minimum Inductor Current Ripple in Multi-winding Coupled Inductor Used in Bidirectional DC-DC Converters