Indium Tin Oxide Gate Electrode Research Articles

Demonstration of p-GaN/AlGaN/GaN High Electron Mobility Transistors With an Indium–Tin–Oxide Gate Electrode

In this study, p-GaN/AlGaN/GaN high electron mobility transistors (HEMTs) with indium-tin-oxide (ITO) gate electrodes are demonstrated. The DC measurements for the devices show a drain current (ID) of 438 mA/mm at a V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> and a V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> of 10 and 8 V, respectively. A maximum gm of 92.1 mS/mm and a specific ON-resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> · A) of 1.86 mΩcm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> are obtained. Furthermore, the robustness of the ITO gate electrode atop the p-GaN layer under the forward gate bias is studied, indicating stable I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> - V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> - V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> characteristics for a gate voltage of less than 11 V, which is higher than the compared device with Ni/Au Schottky gate contact. Therefore, ITO gate electrodes, which are compatible with the Light-emitting diode (LED) process, are a promising alternative for p-GaN HEMT technologies.

Reversible capacitance changes in the MOS capacitor with an ITO/CeO2/p-Si structure

A reversible capacitance changes with respect to the polarity of applied voltage is demonstrated in a MOS (metal-oxide-semiconductor) capacitor consisting of a high-k CeO2 and oxygen-reactive indium-tin-oxide (ITO) electrode on p-Si substrate, i.e., an ITO/CeO2/p-Si structure. The capacitance-voltage (C-V), capacitance-time (C-t), and voltage-pulse measurements exhibit consistently that the accumulation capacitance is gradually increased upon repeatedly applying negative voltage to the ITO, while the depletion capacitance is reversibly decreased upon applying positive voltage. Particularly, the capacitance change is observed even at a low voltage of ±0.5 V from the device with 40-nm-thick CeO2 layer. The capacitance change is further enhanced as increasing measurement temperature from 25 to 100 °C, implying that the capacitance change is associated with the thermally activated process under the applied voltage. In addition, the resistance of ITO gate electrode is found to decrease upon applying negative voltage, but it is increased reversibly upon applying positive voltage. The reversible capacitance changes in the MOS capacitor with oxygen-reactive ITO gate electrode are explained with voltage-driven oxygen ion migration between ITO and CeO2 layers that can alter the CeO2 dielectric permittivity and induce the gate depletion in the ITO. These reversible capacitance changes have a potential to be employed to modulate the MOSFET (MOS field-effect-transistor) properties such as on-state current, threshold voltage, and transconductance.

Quantum Confinement and Interface States in ZnO Nanocrystalline Thin-Film Transistors

The experimental current–voltage ( ${I}_{D}$ – ${V}_{G}$ ) and capacitance–voltage ( ${C}$ – ${V}_{G}$ ) characteristics of the bottom-gate/top-contact ZnO thin-film transistors (TFTs) are analyzed accounting for quantum confinement and interface state effects. All the measurements are performed on the same TFTs composed of a 45-nm-thick nanocrystalline ZnO channel, indium tin oxide gate electrode, and a 21-nm-thick Al2O3 gate insulator. Interface state density (Dit) derived from the combined high–low frequency capacitance method reveals a large Dit near the conduction band edge. The TFT characteristics are simulated using a Schrodinger–Poisson model and compared to a semiclassical model. The Schrodinger–Poisson model calculates a lower C in accumulation by correctly accounting for the peak carrier concentration being several nanometers away from the ZnO/Al2O3 interface. The fit error in ${C}$ – ${V}_{G}$ in strong accumulation is only 1.2% compared to 4% in the semiclassical simulations. All simulations are performed using 21 nm of Al2O3. An effective mobility ( $\mu _{\mathrm{ eff}}$ ) that increases linearly with gate voltage is derived from the ratio of the experimental ${I}_{D}$ and the simulated mobile charge per unit area of the channel. Ignoring quantum confinement overestimates the channel charge and hence underestimates $\mu _{\mathrm{ eff}}$ by 40%. An additional Dit profile, at the top interface of the ZnO, is proposed in our analysis to explain the ${I}_{D}$ – ${V}_{G}$ characteristics in the subthreshold region.

Semi-transparent vertical organic light-emitting transistors

Abstract Vertical organic light-emitting transistor (VOLET) having an organic light-emitting diode integrated with a vertical thin-film transistor is promising for transparent electronics because the vertical device structure potentially offers a display with a large aperture ratio and a low power consumption. However, making a transparent VOLET has been challenging due to the requirements for all transparent electrodes including fabrication of a porous source electrode for current modulation in the device. Here, we report a semi-transparent VOLET with a large modulation of light emitted through the top and bottom electrodes using a nano-porous indium-tin oxide (ITO) source electrode, a Mg:Ag drain electrode, and an ITO gate electrode. The porous ITO source electrode is not only important for luminance modulation, but the nano-textured film morphology also enhances light extraction from the device. Finally, we show that the off current of the VOLET can be suppressed with an electron transporting layer (C60), leading to a large luminance on/off ratio of 104.

Vertical Organic Field-Effect Transistors for Integrated Optoelectronic Applications.

Direct integration of a vertical organic field-effect transistor (VOFET) and an optoelectronic device offers a single stacked, low power optoelectronic VOFET with high aperture ratios. However, a functional optoelectronic VOFET could not be realized because of the difficulty in fabricating transparent source and gate electrodes. Here, we report a VOFET with an on/off ratio up to 10(5) as well as output current saturation by fabricating a transparent gate capacitor consisting of a perforated indium tin oxide (ITO) source electrode, HfO2 gate dielectric, and ITO gate electrode. Effects of the pore size and the pore depth within the porous ITO electrodes on the on/off characteristic of a VOFET are systematically explained in this work. By combining a phosphorescent organic light-emitting diode with an optimized VOFET structure, a vertical organic light-emitting transistor with a luminance on/off ratio of 10(4) can be fabricated.

Organic Field‐Effect Transistor Memory Devices Using Discrete Ferritin Nanoparticle‐Based Gate Dielectrics

Organic field-effect transistor (OFET) memory devices made using highly stable iron-storage protein nanoparticle (NP) multilayers and pentacene semiconductor materials are introduced. These transistor memory devices have nonvolatile memory properties that cause reversible shifts in the threshold voltage (Vth ) as a result of charge trapping and detrapping in the protein NP (i.e., the ferritin NP with a ferrihydrite phosphate core) gate dielectric layers rather than the metallic NP layers employed in conventional OFET memory devices. The protein NP-based OFET memory devices exhibit good programmable memory properties, namely, large memory window ΔVth (greater than 20 V), a fast switching speed (10 μs), high ON/OFF current ratio (above 10(4)), and good electrical reliability. The memory performance of the devices is significantly enhanced by molecular-level manipulation of the protein NP layers, and various biomaterials with heme Fe(III) /Fe(II) redox couples similar to a ferrihydrite phosphate core are also employed as charge storage dielectrics. Furthermore, when these protein NP multilayers are deposited onto poly(ethylene naphthalate) substrates coated with an indium tin oxide gate electrode and a 50-nm-thick high-k Al2 O3 gate dielectric layer, the approach is effectively extended to flexible protein transistor memory devices that have good electrical performance within a range of low operating voltages (<10 V) and reliable mechanical bending stability.

Light Effects on Charge Trapping and Detrapping of nc-ZnO Embedded ZrHfO High-k MOS Nonvolatile Memories

MOS capacitors containing the nanocrystalline ZnO embedded Zr doped HfO2 high-k gate dielectric film integrated with the indium tin oxide gate electrode have been fabricated and characterized under the dark and light exposure conditions for nonvolatile memory properties. When measured in dark, the capacitor had a large charge storage capacity showing a counterclockwise capacitance-voltage hysteresis. When exposed to the light, the memory capacity was increased. The generation and transfer of electrons and holes in and from the nanocrystalline ZnO under the light exposure condition are responsible for the memory window change and charge retention characteristics.

Characteristics of sputtered Al-doped ZnO films for transparent electrodes of organic thin-film transistor

Aluminum-doped ZnO (AZO) thin-films were deposited with various RF powers at room temperature by radio frequency (RF) magnetron sputtering method. The electrical properties of the AZO film were improved with the increasing RF power. These results can be explained by the improvement of the crystallinity in the AZO film. We fabricated the organic thin-film transistor (OTFT) of the bottom gate structure using pentacene active and poly-4-vinyl phenol gate dielectric layers on the indium tin oxide gate electrode, and estimated the device properties of the OTFTs including drain current–drain voltage (I D–V D), drain current–gate voltage (I D–V G), threshold voltage (V T), on/off ratio and field effect mobility. The AZO film that grown at 160 W RF power exhibited low resistivity (1.54 × 10 − 3 Ω·cm), high crystallinity and uniform surface morphology. The pentacene thin-film transistor using the AZO film that's fabricated at 160 W RF power exhibited good device performance such as the mobility of 0.94 cm 2/V s and the on/off ratio of ~ 10 5. Consequently, the performance of the OTFT such as larger field-effect carrier mobility was determined the conductivity of the AZO source/drain (S/D) electrode. AZO films prepared at room temperature by the sputtering method are suitable for the S/D electrodes in the OTFTs.