Quantum Confinement and Interface States in ZnO Nanocrystalline Thin-Film Transistors

Abstract

The experimental current–voltage ( ${I}_{D}$ – ${V}_{G}$ ) and capacitance–voltage ( ${C}$ – ${V}_{G}$ ) characteristics of the bottom-gate/top-contact ZnO thin-film transistors (TFTs) are analyzed accounting for quantum confinement and interface state effects. All the measurements are performed on the same TFTs composed of a 45-nm-thick nanocrystalline ZnO channel, indium tin oxide gate electrode, and a 21-nm-thick Al2O3 gate insulator. Interface state density (Dit) derived from the combined high–low frequency capacitance method reveals a large Dit near the conduction band edge. The TFT characteristics are simulated using a Schrodinger–Poisson model and compared to a semiclassical model. The Schrodinger–Poisson model calculates a lower C in accumulation by correctly accounting for the peak carrier concentration being several nanometers away from the ZnO/Al2O3 interface. The fit error in ${C}$ – ${V}_{G}$ in strong accumulation is only 1.2% compared to 4% in the semiclassical simulations. All simulations are performed using 21 nm of Al2O3. An effective mobility ( $\mu _{\mathrm{ eff}}$ ) that increases linearly with gate voltage is derived from the ratio of the experimental ${I}_{D}$ and the simulated mobile charge per unit area of the channel. Ignoring quantum confinement overestimates the channel charge and hence underestimates $\mu _{\mathrm{ eff}}$ by 40%. An additional Dit profile, at the top interface of the ZnO, is proposed in our analysis to explain the ${I}_{D}$ – ${V}_{G}$ characteristics in the subthreshold region.