Abstract

This paper presents a study on the performance of a bottom gate ZnO thin film transistor (TFT) model through 2-D TCAD device simulations and proposes a surface potential analytical model for the same. The simulation has been calibrated with a fabricated ZnO TFT. The analytical model is found to be in good agreement with the simulated measurements. Through further analyses on TCAD tool, the electrical characteristics of ZnO TFT have been investigated to comprehensively deduce the effect of ZnO active layer thickness, the dielectric material and the drain voltage. To obtain a significant ratio of on and off currents, and a positive gate voltage switching, gate workfunction engineering has been demonstrated.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.