Indium Bump Research Articles

Indium Bump Bonding: Advanced Integration Techniques for Low-Temperature Detectors and Readout

We have examined the influence of bump shape and bonding pressure on low-temperature electrical properties of indium bump connections including superconducting transition temperature, normal state resistance, and superconducting critical current. We describe our test structures, bonding process, and methods of characterization. At temperatures below 1 K, we observe critical currents greater than 70 mA for indium bump connections with a nominal bump size of 17 µm × 17 µm.

Fabrication and bonding of In bumps on Micro-LED with 8 μm pixel pitch

Indium (In) is currently used to fabricate metal bumps on micro-light-emitting diode (Micro-LED) chips due to its excellent physical properties. However, as Micro-LED pixel size and pitch decrease, achieving high-quality In bumps on densely packed Micro-LED chips often presents more challenges. This paper describes the process of fabricating In bumps on micro-LEDs using thermal evaporation, highlighting an issue where In tends to grow laterally within the photoresist pattern, ultimately blocking the pattern and resulting in undersized and poorly dense In bumps on the Micro-LED chip. To address this issue, we conducted numerous experiments to study the height variation of In bumps within a range of photoresist aperture sizes (3 μm −7 μm) under two different resist thickness conditions (3.8 μm and 4.8 μm). The results showed that the resist thickness had a certain effect on the height of In bumps on the Micro-LED chip electrodes. Moreover, we found that, with the photoresist pattern size increasing under constant resist thickness conditions, the height and quality of the bumps significantly improved. Based on this finding, we rationalized the adjustment of the photoresist pattern size within a limited emission platform range to compensate for the height difference of In bumps caused by different resist thicknesses between the cathode and anode regions. Consequently, well-shaped and dense In bumps with a maximum height of up to 4.4 μm were fabricated on 8 μm pitch Micro-LED chips. Afterwards, we bonded the Micro-LED chip with indium bumps to the CMOS chip, and we found that we could successfully control the CMOS chip to drive the Micro-LED chip to display specific characters through the Flexible Printed Circuit (FPC). This work is of significant importance for the fabrication of In bumps on Micro-LED chips with pitches below 10 μm and subsequent bonding processes.

Evaluation of flip-chip bonding electrical connectivity for ultra-large array infrared detector.

Flip-chip bonding is a key technology for infrared focal plane array (IRFPA) detectors. Due to the high cost of device preparation, the ultra-large array infrared detector cannot be directly used for the flip-chip bonding experiment, and the connectivity rate cannot be measured. To evaluate the flip-chip bonding process, a test device which has the same interconnecting structure as current IRFPA detectors is proposed. Indium bumps are electrically extracted to test electrodes. Electrical measurements were performed to characterize the connection and adhesion of the indium bumps and to calculate the connectivity rate. The electrical connectivity characteristics of the test devices correspond to the observation results of the indium bump extrusion, effectively detecting the interconnecting anomalies such as disconnection, adhesion, overall misalignment, etc., and verifying the feasibility of the test method. The test device has similar multi-layer components and thermal properties as HgCdTe infrared detector for process evaluation and post-processing experiment. The connectivity rate of the test device is up to 100%, and remains above 99% after thermal recycle experiment. The contact resistance of the interconnecting structure is calculated to be about 31.84 Ω based on the test results.

Deposition of Fine-Pitch Indium Bumps on Single Die

Photolithographic lift-off at wafer level is a wellestablished method for depositing indium bumps onto pixels of electronic components such as sensors and application-specific integrated circuits (ASIC). These indium bumps form interconnects between pixels of the components during flip-chip bonding to make devices such as radiation detectors. Such components are not always available on wafer-scale, and single dies need to be processed in small-scale production, R&D, or for Cd(Zn)Te detector material. Photolithography on single dies is ineffective due to the edge-bead of photoresist that compromises perfect indium deposition onto pixels near the periphery of the die. To utilize the maximum surface area of a die, a rigid mask with apertures (shadow mask) is an adequate substitute for the photoresist. Different mask designs and production techniques for fine-pitch indium bump arrays are investigated by testing electroformed stencils or micromachined silicon (Si) membranes as shadow masks. For the indium deposition, the sensor and ASIC dies are clamped into custom-made jigs that include shadow masks. Alternatively, dies can be adhered to shadow masks with soluble adhesive. The apertures of a mask are aligned to the pixel array of the detector component. Bump arrays with 250μm- and 100μm-pitch were demonstrated with electroformed stencils. For smaller pitch (55μm) and bump diameter of ~20μm, specialized masks from Si membranes are tested. Components with successfully deposited indium bump arrays were subsequently flip-chip bonded at room temperature without reflowing the indium. A bond yield of at least 99.9% pixels for such flip-chip bonded radiation detector was shown using the read-out signal from exposure with a flat field X-ray radiation of an Am-241 sealed source.

Fine Pitch Micro Indium Bump Interconnect Flip Chip Bonding

Quantum computing processors, micro LED displays and Focal Plane Array (FPA) imaging and detector devices such as infrared (IR) thermal imaging sensors are seeing higher demand as more practical applications requiring these components are coming into research and development, industrial, military and consumer markets. This paired with higher pixel and Qubit count and interconnect density, on larger and larger chips is driving hybridization and monolithic integration in these technologies. This is showing a marked increase in demand for fine pitch micro bump interconnection flip chip die bonding. However, some critical challenges facing these technologies are; larger component sizes mean higher density interconnections over increasing surface area. Submicron accuracy required to align fine pitch micro interconnect arrays. This together with the challenges facing the materials that are becoming the industry standard for these applications, such as the requirement for the assembled components to remain stable in extreme conditions such as cryogenic application environments. Combined with low loss high strength mechanical/ electrical interconnect requirements on components containing sensitive materials, structures and unmatched coefficient of thermal expansion (CTE) means that processing gases such as formic acid or high temperature reflow bonding can no longer be used to bond these devices. These challenges mean that the industry is fast approaching the limitations of even state-of-the-art die bonders and die bonding methods on the market today. This paper is going to highlight these challenges and the methods used to address them to produce large format, high density IR thermal imaging FPA devices, Quantum processors and micro LED displays using fine pitch micro Indium bump array interconnections that meet today’s industry requirements.

Reliability Assessment of Indium Micro Bumps for 2.5D/3D Electronic Packaging through Cryo-Argon Milling Technique

Indium bumps are widely used in electronic packaging for interconnecting microelectronic devices due to their low melting point of 156.6°C, excellent bonding capabilities at room temperature, high thermal conductivity, ductility at extremely low temperatures, and ability to compensate for the mismatched coefficient of thermal expansion (CTE) between different materials. However, cross-sectioning indium bumps can be challenging due to the softness and low melting point of indium. The cutting tools and techniques used must be optimized for the specific sample being analyzed, and specialized preparation techniques such as cryogenic freezing or chemical etching may be required, which can be expensive and time-consuming. Cryo-Focused Ion Beam (FIB) is also a technically demanding process that requires careful optimization of milling parameters, multiple iterations of milling and imaging, specialized equipment, and expertise, which can make it too expensive. It should be noted that the maximum achievable cross-sectional area with cryo-FIB is limited, typically in the range of hundreds of micrometers. Cryo-Argon milling is an effective technique for obtaining high-quality cross-sections of indium bumps arrays and other materials prone to deformation or melting during traditional cross-sectioning. This process involves freezing the sample using liquid nitrogen and bombarding it with a stream of Argon gas ions, which reduces the deformation and melting of the indium. This paper presents challenges related to sample preparation and mechanical polishing for Ar milling technique, and we provide key solutions to these challenges to obtain millimeter-wide and damage-free cross-sections of arrays of indium micro bumps.

Chemical mechanical polishing for indium bond pad damascene processing

We investigated chemical mechanical polishing (CMP) of indium, with the goal of obtaining indium bond pads for later cryo-3D integration of quantum computing-related chips, through bonding between these bond pads and indium bumps. Higher removal rates were obtained with soft CMP pads than with hard pads. The latter led to deep scratching, while this effect was much more limited for soft pad CMP. On patterned wafers, indium is cleared well in structured areas using soft pad CMP, leading to relatively high-quality indium surfaces inside bond pads, although corrosion might be of some concern. Pattern density uniformity was an important factor for within-die deviation in indium clearing time. Dishing was much more limited than in earlier work on indium polishing, while surface roughness was also found to be relatively limited. The obtained indium damascene bond pads may be suitable for 3D die-to-die and wafer-to-wafer bonding through indium pad-to-bump bonding.

Reliability Assessment of Indium Micro Bumps for 2.5D/3D Electronic Packaging Through Cryo-Argon Milling Technique

Indium bumps are widely used in electronic packaging for interconnecting microelectronic devices due to their low melting point of 156.6 degrees C, excellent bonding capabilities at room temperature, high thermal conductivity, ductility at extremely low temperatures, and ability to compensate for the mismatched coefficient of thermal expansion between different materials. However, cross-sectioning indium bumps can be challenging due to the softness and low melting point of indium. The cutting tools and techniques used must be optimized for the specific sample being analyzed, and specialized preparation techniques such as cryogenic freezing or chemical etching may be required, which can be expensive and time-consuming. Cryo-focused ion beam (FIB) is also a technically demanding process that requires careful optimization of milling parameters, multiple iterations of milling and imaging, specialized equipment, and expertise, which can make it too expensive. It should be noted that the maximum achievable crosssectional area with cryo-FIB is limited, typically in the range of hundreds of micrometers. Cryo-Argon milling is an effective technique for obtaining high-quality cross-sections of indium bump arrays and other materials prone to deformation or melting during traditional crosssectioning. This process involves freezing the sample using liquid nitrogen and bombarding it with a stream of Argon gas ion, which reduces the deformation and melting of the indium. This paper presents challenges in the sample preparation and mechanical polishing of indium micro bumps. We are showcasing an artifact: polishing particles embedded in the indiummicro bumps, hindering the revelation of their microstructure. To address this issue, we are incorporating cryo-Ar milling to remove the embedded particles from the surface of indium micro bumps. This work presents data before and after the application of cryo-Ar milling, demonstrating a significant improvement in the microstructure of indium micro bumps. Millimeter-wide, damage-free cross-sections of arrays of indium micro bumps with a clean and smooth surface were achieved through cryo-Argonmilling at270 degrees C.

Electrodeposited Nanowires for High Density Interconnects of GaN-Based MicroLEDs

For next-generation applications, fully controllable gallium nitride (GaN)-based micro light emitting diode (microLED) arrays will play a crucial role. These feature high pixel densities, high intensities, and high efficiencies. Well-established top-down etching processing schemes of pristine LED wafers allow for an easily accessible and scalable fabrication approach for microLED arrays down to the single digit µm dimensions with dies featuring several 100,000 on a square centimeter. At this scale, classical bonding approaches like wire bonding fail to harvest the true potential of such an array due to inherit technological restrictions. To allow for the individual controllability of every pixel a highly scalable integration approach to a CMOS backplane is necessary. Established processes for the realization of such an integration often feature major drawbacks. Indium bumps deposited via thermal evaporation generally fulfill the scale requirements but fail to adapt to the unique challenges of such hybrid integration. High non-planarity of the substrate, high wafer bow, and mismatching thermal expansion coefficients can lead to diminishing bonding yields and hence functioning microLEDs during the high-temperature bonding step necessary for indium bumps. Additionally, Indium is an inferior electrical and thermal conductor to other metals and limits the active performance of the device while also restricting its usage area due to its low melting point. In the currently ongoing EU Project SMILE, we are developing GaN-based microLED arrays up to 512 x 512 pixels and thoroughly examine established bonding technologies as well as an in-house developed metal nanowire approach. The necessary perquisites for electrochemical deposition, namely the conductive seed and the removal thereof can easily be integrated into the device’s processing scheme. Nanowires are electrochemically deposited out of a liquid solution at room temperature onto the microLED array and the CMOS backplane. The direction, length, and diameter of the nanowires can easily be controlled to accustom different proportions and bonding geometries. Inline monitoring via the recorded amperogram allows for the differentiation of the individual stages of nanowire growth during the electrochemical deposition. Mechanically stable and electrically sufficient interconnects can then be realized by pressing the nanowires of both substrates into each other. The high aspect ratio of the wires results in a high surface area and allows for nanowires of both substrates to intertwine forming stable connections with large contact surfaces at low pressures without any additional heating steps necessary. Due to the variability of the wire length and ongoing intertwining during the bonding, non-planarities and wafer bow can be accommodated. This flexible bonding behavior is a unique advantage of bonds based on metal nanowires. The junctions approach the conductivity of bulk material and are crucial for the thermal management of the microLED array. The final LED device generates a substantial amount of heat, which cannot be cooled meaningfully via convection to the surrounding air or by its radiation. Consequently, a capable thermal conduction towards the silicon chip is necessary for heat management. Here the metal nanowires play a crucial role in providing this thermal connection via the bonding interface, which potentially allows for improved device performance over other bonding technologies.

Thermal resistance in superconducting flip-chip assemblies

Cryogenic microsystems that utilize different 3D integration techniques are being actively developed, e.g., for the needs of quantum technologies. 3D integration can introduce opportunities and challenges to the thermal management of low temperature devices. In this work, we investigate sub-1 K inter-chip thermal resistance of a flip-chip bonded assembly, where two silicon chips are interconnected by compression bonding via indium bumps. The total thermal contact area between the chips is 0.306 mm2, and we find that the temperature dependence of the inter-chip thermal resistance follows the power law of αT−3, with α=7.7–15.4 K4μm2/nW. The T−3 relation indicates phononic interfacial thermal resistance, which is supported by the vanishing contribution of the electrons to the thermal conduction, due to the superconducting interconnections. Such a thermal resistance value can introduce a thermalization bottleneck in particular at cryogenic temperatures. This can be detrimental for some applications, yet it can also be harnessed. We provide an example of both cases by estimating the parasitic overheating of a cryogenic flip-chip assembly operated under various heat loads as well as simulate the performance of solid-state junction microrefrigerators utilizing the observed thermal isolation.

A simple way to predict the flip–chip gap

Using laser scanning confocal microscopy measurement, a concise method for extracting the indium bump shape in microelectronics was first established. The extracted bump shape was then used as the input for finite element analysis. The modeled one-bump deformation was used to predict the final flip–chip gap after bonding. Dovetailed with the results of cross-sectional scanning electron microscopy, this simple and non-destructive method for predicting a flip–chip gap of the order of 10 microns or less was eventually validated.

Bump deposition techniques for hybrid X-ray detectors

Flip-chip bonding is a common method for joining application-specific integrated circuits (ASIC) to pixel sensors in order to build hybrid radiation detectors for X-rays and gamma-rays. STFC-RAL is using two methods for the interconnects between ASIC and sensor pixels. These are either indium bumps which are deposited on ASIC and sensor prior to bonding or alternatively electrically conductive adhesive dots are printed on the sensor pixel array and flip-chip bonded to gold studs attached to each pixel of the ASIC. Conventionally the indium deposition is carried out on wafer-scale using a photolithographic lift-off process. Sensor and ASIC with indium bumps are singulated from wafers afterwards. Some sensor material (e.g. CdZnTe) which is required for high-energy and high-flux X-ray detectors at X-ray Free Electron Lasers (XFEL) or in other scientific experiments is only available as individual die instead of wafers. The stencil printing of conductive epoxy dots onto those sensor dies together with gold ball studding of ASICs is a suitable method for those dies. However, due to the size of printed epoxy dots this method has a limited pixel pitch and is currently only used for sensors with 250 μm-pitch or for larger pitch. A novel method for indium deposition was developed for such dies. A shadow mask with small apertures is optically aligned to the pixel array and mechanically clamped to the sensor die. After indium evaporation onto this assembly and after removal of the mask, indium bumps as small as 50 μm with a height of ∼ 5 μm are deposit onto the pixel array of the sensor. The same is done for a matching ASIC. A comparison of these two methods indicates that indium bumps created by the shadow mask technique are approx. half the size of the epoxy dots and comparable with gold studs. Using this method, at present a pitch of 100 μm for those indium bumps can be achieved and development for further improvement towards smaller pitch is carried out currently. This novel indium deposition method is compared with the conventional wafer-scale indium lift-off method and the epoxy/gold stud flip-chip bonding in terms of interconnect quality, bond yield, and suitability for hybrid radiation detectors.

Modeling Insights Into the Assembly Challenges of Focal Plane Arrays

Ongoing technological advances in photodetector material growth and processing, readout integrated circuits, and robust hybridization (packaging) methods for assembling high-resolution and small-pitch size pixel arrays are the main enabling factors for pushing the frontiers of high-performance Focal Plane Array (FPA) technologies for imaging systems. This paper details the development of analytical and numerical models and demonstrates their use to generate insights into the feasibility of two flip-chip assembly processes for packaging infrared (IR) detector chips. The modelling studies focus on the challenges of forming the indium interconnection arrays in the case of the FPA technologies using Group III-V compound semiconductor materials and ultra-fine pitch pixel array layouts. The accurate alignment of the IR detector chip onto the readout chip in the case of high-density pixel architectures is a critical requirement for the packaging process. To gain better understanding of this requirement, which has a clear implication for the quality and subsequent reliability performance of the FPA, compression and reflow bonding process models are developed using suitable modeling approaches and methods and then demonstrated for two distinctive focal plane array design configurations. The novelty of this work is in the developed modeling capabilities utilizing different computational methods, from large deformation and contact analysis finite element to energy-based and harmonic motion mechanics, to characterize and optimize the mechanical and dynamic non-linear behavior of the indium solder joints and their formation during FPA packaging. The feasibility of bonding techniques for different resolution FPAs and under flip-chip misalignment conditions is assessed. The modeling results pointed to a very strict, sub-micrometer flip-chip placement accuracy requirement for the assembly of FPAs with ultra-fine indium bump array resolution.

A Novel MCT Focal Plane Array Thermally Stressed at Low Temperatures

The <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mercury-cadmium-telluride</i> (MCT) focal plane arrays (FPA) have being populating most of the ground and space instrumentation devoted to near- and short-wave infrared (NIR-SWIR) during the last decades. The ASTEROID project is a fully European initiative to achieve a local manufacturer ready to develop MCT FPAs of ≥ 2k2 class. In order to test and characterize such detectors, special facilities are demanded. In this way, the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Institut de Física d’Altes Energies</i> (IFAE) has conducted a research to validate the hybridization reliability of the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">readout integrated circuit</i> (ROIC) and the MCT detector, which is performed through indium bumps soldering technique. The hybridization reliability was measured by subjecting the ASTEROID detector to several thermal cycles in a temperature range that surpass the detector operating temperature. At every individual thermal cycle, a set of images was captured, analyzed and compared each other to track any pixel degradation. Finally, making use of image classification and segmentation algorithms, the measured number of damaged pixels was determined and the results are presented in this paper.

Electrochemical deposition of indium from chloride bath for low-temperature microbump bonding

Indium chloride bath was characterized towards the application of low-temperature thermal compression bonding. The electrochemical behavior of the indium chloride bath was analyzed using the cyclic voltammetry method. Electrochemical deposition of indium was carried out at various deposition factors on different materials such as copper, nickel, and cobalt. Based on the results of indium deposition obtained from the blanket films, indium bumps were electrochemically fabricated inside a through-resist hole pattern at various current densities. In addition, stacked indium bumps with various metals (Cu/In, Cu/Ni/In, Cu/Co/In) were formed for a practical application of micro bump bonding. Moreover, the formation of the intermetallic compounds between indium and under bump metallization was investigated.

Vacuum-gap transmon qubits realized using flip-chip technology

Significant progress has been made in building large-scale superconducting quantum processors based on flip-chip technology. In this work, we use flip-chip technology to realize a modified transmon qubit, denoted as the “flipmon,” whose large shunt capacitor is replaced by a vacuum-gap parallel plate capacitor. We place one of the qubit pads and a single Josephson junction on the bottom chip and the other pad on the top chip, which is galvanically connected with the junction through an indium bump. The electric field energy participation ratio can arrive at nearly 53% in air when the vacuum-gap is about 5 μm, thus potentially leading to a lower dielectric loss. The coherence times of the flipmons are obtained in the range of 30–60 μs, which are comparable with that of conventional transmons with similar fabrication processes. The electric field simulation indicates that the metal-air interface's energy participation ratio increases significantly and may dominate the flipmon's decoherence. This suggests that more careful surface treatment needs to be considered. No evidence shows that the indium bumps inside the flipmons cause significant decoherence. With well-designed geometry and good surface treatment, the coherence of the flipmons can be further improved.

Development of a High Performance 1280×1024 InGaAs SWIR FPA Detector at Room Temperature

A 1280 × 1,024 In0.53Ga0.47As short wave infrared (SWIR) focal plane array (FPA) detector with a planar-type back-illuminated process has been fabricated. With indium bump flip-chip bonding techniques, the InGaAs photodiode arrays were hybrid-integrated to the CMOS readout integrated circuit (ROIC) with correlated double sampling (CDS). The response spectrum is 0.9–1.7 μm. The test results show that the dark current density is 2.25 nA/cm2 at 25 °C, the detectivity D* is up to 1.1 × 1013 cm · Hz1/2/W, the noise electron is as low as 48 e− under correlated double sampling mode, the quantum efficiency is 88% at 1550 nm, and the operability is more than 99.9%. Moreover, the dark current and noise electron have been studied theoretically in depth. The results indicate that the diffusion current is the main contribution of the dark current, and the readout integrated circuit noise electron is the main source of FPA noise.

Indium-Based Micro-Bump Array Fabrication Technology with Added Pre-Reflow Wet Etching and Annealing.

Indium-based micro-bump arrays, among other things, are used for the bonding of infrared photodetectors and focal plane arrays. In this paper, several aspects of the fabrication technology of micrometer-sized indium bumps with a smooth surface morphology were investigated. The thermal evaporation of indium has been optimized to achieve ~8 μm-thick layers with a small surface roughness of Ra = 11 nm, indicating a high packing density of atoms. This ensures bump uniformity across the sample, as well as prevents oxidation inside the In columns prior to the reflow. A series of experiments to optimize indium bump fabrication technology, including a shear test of single columns, is described. A reliable, repeatable, simple, and quick approach was developed with the pre-etching of indium columns in a 10% HCl solution preceded by annealing at 120 °C in N2.

A study on the surface correction of large format infrared detectors

Large format hybrid infrared focal array detectors, which require a wide range and high resolution, are of significant technical importance for earth observation systems and scientific space programmes. A typical large hybrid infrared focal plane array (IRFPA) detector formed by a detector chip is directly hybridized to a silicon readout integrated circuit (Si-ROIC) via indium bumps. However, for a large format IRFPA detector, the connection rate of the indium bumps strongly depends on the warpage of the Si-ROIC and the detector chip, which usually results from technological processes. In this paper, a surface correction structure is proposed to optimize the warpage of the Si-ROIC and the detector chip before flip-chip. The warpage of the Si-ROIC is analysed by the finite element method. The simulation results are in good agreement with the experiment. After optimization, the warpage of a 2048 × 2048 Si-ROIC decreased from 13 μm to less than 3 μm. Thus, it is beneficial to improve the IRFPA bump connection rate. Compared with traditional growth stress films, this method is more flexible and has easy accessibility. Eventually, it could enhance the stability of the large format IRFPA detector.

High coherence superconducting microwave cavities with indium bump bonding

Low-loss cavities are important in building high-coherence superconducting quantum computers. Generating high-quality joints between parts is crucial for the realization of a scalable quantum computer using the circuit quantum electrodynamics (cQED) framework. In this paper, we adapt the technique of indium bump bonding to cQED to realize high-quality superconducting microwave joints between chips. We use this technique to fabricate compact superconducting cavities in the multilayer microwave integrated quantum circuit (MMIQC) architecture and achieve single photon quality factors over 300 × 106 or single-photon lifetimes approaching 5 ms. To quantify the performance of the resulting seam, we fabricate microwave stripline resonators in multiple sections connected by different numbers of bonds, resulting in a wide range of seam admittances. The measured quality factors combined with the designed seam admittances allow us to bound the conductance of the seam at gseam≥2×1010/(Ω m). Such a conductance should enable the construction of micromachined superconducting cavities with a quality factor of at least a billion. These results demonstrate the capability to construct very high-quality microwave structures within the MMIQC architecture.