Independent Double Gate Research Articles

Ultra‐efficient fully programmable membership function generator based on independent double‐gate FinFET technology

SummaryThis paper demonstrates an ultra‐efficient, fully programmable membership function generator (MFG) utilizing independent double‐gate (IDG) FinFET technology. The proposed MFG can produce s‐shaped, z‐shaped, triangular, and trapezoidal membership functions. By employing only six transistors, the designed MFG provides full controllability over the height, position, width, and slope of the generated waveforms. Without using any additional transistor and changing the dimensions, the proposed MFG can calibrate the slope of the output based on the back‐gate bias voltage of the IDG‐FinFETs. According to our extensive simulations, the proposed MFG shows promising improvements in transistor count (70%), power‐delay‐product (PDP) (80%), and maximum absolute error (61%) as compared with its state‐of‐the‐art counterparts. To benchmark the functionality of the proposed MFG in practical applications, our generated membership function is exploited as the neuron's activation function in a multilayer perceptron (MLP) neural network. The simulation results indicate that the training process of the simulated MLP with the proposed MFG closely tracks the results obtained from the ideal MLP with the sigmoid activation function. A figure of merit (FoM) is defined considering the hardware efficiency and accuracy of the neural networks to evaluate the entire performance of the proposed MFG. The FoM simulations demonstrate that the proposed MFG presents an excellent trade‐off between hardware performance and accuracy in neural network applications. Our results emphasize that the proposed MFG is a potential candidate for designing high‐performance on‐chip neural networks.

Design of Universal Logic Gates using Homo and Hetero-Junction Double Gate TFETs with Pseudo-Derived Logic

This work explores homo and hetero-junction Tunnel field-effect transistor (TFET) based NAND and NOR logic circuits using 30 nm technology and compares their performance in terms of power consumption and propagation delay. By implementing homo-junction TFET based NAND and NOR logic circuits, it has been observed that NAND consumes less power than NOR gate, since current drawn by PTFET in pull-up network of NOR gate is higher. The delay of homo-junction TFET based NOR logic gate is lesser than that of NAND gate due to its reduced internal capacitances. To meet the enhanced performance of both NAND and NOR logic circuits, shorted and independent double gate hetero-junction (GaSb-InAs) TFETs are designed and implemented. In order to reduce both power consumption and delay further, Pseudo-derived logic is implemented in NAND and NOR logic circuits for the first time. Hetero-junction TFET based NAND with Pseudo-derived logic circuit shows lesser propagation delay of 103 times and reduction in power consumption by 0.75 times compared to hetero-junction NAND logic circuit. Hetero-junction TFET based NOR with Pseudo-derived logic shows that the reduction in power consumption is of 103 times and less propagation delay than that of hetero-junction NOR logic circuit.

Leveraging Independent Double-Gate FinFET Devices for Machine Learning Classification

Mixed-signal machine learning (ML) classification has recently been demonstrated as an efficient alternative for classification with power expensive digital MOSFET circuits. In this paper, a topology based on independent double-gate (IDG) FinFET devices is proposed for classifying high-dimensional input data into multi-class output space with less power and area as compared with state-of-the-art MOSFET classifiers. To facilitate a high-resolution multiplication as a part of the classifier predictions, ML features and feature weights are, respectively, fed to the back and front gate inputs of the individual IDG-FinFET transistors. A classifier that considers the decisions of the individual predictors is designed at 30 nm FinFET technology node and operates at 333 MHZ with nominal supply voltage of one volt. To evaluate the performance of the classifier, a reduced MNIST dataset is generated. The original resolution is reduced from $28 \times 28$ features to $9 \times 9$ features and the most important features are selected with sequential backward selection algorithm. The system is simulated in SPICE, exhibiting prediction accuracy of 90%, energy consumption of 25 pJ per classification (over four times lower than similar state-of-the-art classifiers), area of 1,365 ${\mu }\text {m}^{2}$ , and a stable response under a wide range of system variations.

Reduced interfacial fluctuation leading enhanced mobility in a monolayer MoS2 DG FET under low vertical electric field

Compared to the silicon device whose performance is severely degraded due to the pin-holes and channel inactive space when the channel thickness is less than 1 nm, despite monolayer transition-metal dichalcogenides being the most stable structure to be used as a two-dimensional semiconductor material, precise analysis of the double-gate (DG) field-effect transistor (FET) device structure has hardly been performed thus far. Hence, we analyzed the device operation characteristics of single-gate and DG sweeps in a monolayer MoS2 DG FET structure, where the interfacial carrier behavior is distinguished from both gates by the different gate dielectric materials at the top and bottom. The synchronized DG sweep operation with biasing of VTG and VBG (=10 VTG) increased the carrier mobility by a factor of 4.85 compared with the independent DG sweep. Direct-current analysis and low-frequency noise modeling indicate that the device performance improves under equivalent gate voltages from both sides, because the device operates in a low vertical electric field and the interfacial carrier fluctuation effect is significantly reduced.

Topological variation on sub-20 nm double-gate inversion and Junctionless-FinFET based 6T-SRAM circuits and its SEU radiation performance

Introduction of new conduction mechanism called junctionless in MOSFETs takes us to another direction in device fabrication. Moving from inversion to junctionless devices in nanoscale regime proves a good alternative for low-power applications and overcomes the barrier of lightly doped channels. 6T-SRAM circuits, the first to arrive in the market long ago, still occupy its area in modern-day ICs too. In this work, four topologies of 6T-SRAM namely Flex-Vth, Flex-PG, PG-SN, and FinFETs are generated based on inversion type independent double-gate as well as common double-gate devices. For the first time, the same four topologies are also generated using junctionless devices. In nanoscale range, the reliability of circuits is given paramount importance since they are easily affected by radiation. This 6T-SRAM's radiation sensitivity is studied and from our simulation results, the common double-gate based 6T-SRAM shows good performance over the independent double-gate based 6T-SRAM in both inversion and junctionless type.

Fin-Width Effects on Characteristics of InGaAs-Based Independent Double-Gate FinFETs

We report the characteristics of InGaAs-based independent double-gate FinFETs with Al2O3/LaAlO3 as gate dielectric. The device can be operated in three different modes ( i.e., single-, double-, and independent double-gate) made possible by the physically separated two sidewall gates. When the device is operated in the double-gate mode, it exhibits better performance in terms of the On/Off current ratio, subthreshold swing, Off current, and channel mobility than in the single-gate mode. In addition, independent double-gate operation makes it possible to modulate channel properties by applying a bias at the opposite gate via gate coupling effects. Our systematic measurements reveal that gate control and coupling effects are enhanced with reduced fin width.

Impact of fin length on threshold voltage modulation by back bias for Independent double-gate tunnel fin field-effect transistors

We investigated the impact of fin length (Tfin) on the threshold voltage (Vth) modulation by back bias (Vb) for independent double-gate (IDG) tunnel fin field-effect transistors (tFinFETs). It was found that Vth can be tuned by Vb for IDG tFinFETs regardless of Tfin, which can be explained by the back-gate-effect model of IDG FinFETs. For IDG tFinFETs, the slope (back-gate-effect factor (γ)) of Vth with respect to Vb increases with thinning Tfin. This means that Tfin thinning is effective for tuning Vth by Vb for IDG tFinFETs. Furthermore, it was demonstrated that this back-bias-effect is consistent with the results of device simulation using an advanced nonlocal band-to-band model.

Ambipolar Independent Double Gate FET (Am-IDGFET) for the Design of Compact Logic Structures

Among potential candidates to replace the CMOS transistor channel, several materials such as CNTs, GNRs, and SiNW show an interesting behavior known as “Ambipolarity.” Ambipolarity, means that n- and p-type behavior can be observed in the same device. By adding a fourth terminal to control the ambipolarity, a new category of devices has seen the light under the name of Ambipolar Independent Double Gate FETs “Am-IDGFETs.” These devices are capable of operating as either n-type or p-type switches according to their back-gate bias voltage. As a result, more options are available with no counterparts in CMOS technology. Based on Am-IDGFETs, we propose a circuit design approach to achieve compact logic structures by merging every two transistors in series structure using the in-field controllability via the back-gate of ambipolar devices. The approach is demonstrated for two logic styles: with a complementary static logic design style, it demonstrates an efficiency that can improve the compactness of logic structure by a factor of 2x, while with a dynamic logic style, a gain of 30% in terms of transistors count is achieved for a variety of application scenarios. We evaluate the performances of circuits designed from this approach in a case study focused on double gate carbon nanotube FET technology. Simulations results show that, with respect to conventional CMOS-16 nm gates and for comparable power consumption, time delay and integration density can both be improved by a factor of 2x and 2.5x, respectively. The power-delay-product is improved by 30%.

Investigation of p-type junction-less independent double-gate poly-Si nano-strip transistors

In this study, novel independent double-gate (IDG) junction-less (J-less) polycrystalline silicon (poly-Si) nano-strip transistors have been fabricated and investigated. Inversion-mode (IM) IDG poly-Si nano-strip transistors with the undoped channel have also been fabricated for comparison. The experimental data show the superior on-state current of J-less transistors over that of IM transistors mainly due to the reduction of the channel resistance (Rch). However, the drain-induced barrier lowering of the J-less transistors is larger than that of IM transistors but the double-gate (DG) configuration can mitigate this problem to some extent. Besides, the subthreshold swing and its fluctuation of the J-less transistors are worse than those of IM transistors under the single-gate operation. Fortunately, this issue can be significantly improved by the aid of DG configuration according to our experimental results. We also demonstrate the possibility of changing the threshold voltage (Vth) under IDG operation for the J-less IDG nano-strip transistors.

Continuity equation based nonquasi-static charge model for independent double gate MOSFET

Using the numerical device simulation we show that the relationship between the surface potentials along the channel in any double gate (DG) MOSFET remains invariant in QS (quasistatic) and NQS (nonquasi-static) condition for the same terminal voltages. This concept along with the recently proposed `piecewise charge linearization' technique is then used to develop the intrinsic NQS charge model for a Independent DG (IDG) MOSFET by solving the governing continuity equation. It is also demonstrated that unlike the usual MOSFET transcapacitances, the inter-gate transcapacitance of a IDG-MOSFET initially increases with the frequency and then saturates, which might find novel analog circuit application. The proposed NQS model shows good agreement with numerical device simulations and appears to be useful for efficient circuit simulation.

Functions classification approach to generate reconfigurable fine-grain logic based on Ambipolar Independent Double Gate FET (Am-IDGFET)

Am-IDGFET is a new family of particular devices in view of the fact that it associates three benefits: (i) it is usually a 1-D electronic device (CNT or SiNW), meaning high mobility, achievable current density and high ION/IOFF ratio; (ii) Independently controlled gates which offers the device extra logic options; (iii) ambipolar behaviour opens the way for N- and P-type polarities in the same device via its back gate. The creativity of this work consists of looking at this new class of emerging technology as an opportunity for new design paradigms with no equivalent counterparts in CMOS technology. Nevertheless, to build a feasible and complete picture of ambipolar logic, innovative design approaches and tools are required. In this paper, we exploit functional classification, a powerful tool for the construction and analysis of Boolean functions, to build reconfigurable logic blocks by defining a hierarchical correlation between structures of functions classes with ambipolar devices. We demonstrate how this approach enables us to build Am-I DGFET-based n-input reconfigurable cells. Several dynamically reconfigurable 2-inputs logic cells with partial and full functionality are designed in this paper. We evaluate the performances of circuits designed from this approach in a case study focused on Double Gate Carbon Nanotube FET (DG-CNTFET) technology. Simulations results show efficiency to build fine grain reconfigurable cells with partial functionality. In the case of 9-functions reconfigurable cell, an improvement of 1.8X in terms of power delay product (PDP) is proved when compared to a CMOS-16nm technology. Fewer control signals are required and the area is reduced by 35% over CMOS technology.

A replacement of high-k process for CMOS transistor by atomic layer deposition

A replacement of high-k process was implemented on an independent double gate FinFET, following the ordinary gate-first process with minor modifications. The present scheme involves neither exotic materials nor unprecedented processing. After the source/drain process, the sacrificial gate oxide was selectively substituted with amorphous Ta2O5 via conformal plasma enhanced atomic layer deposition. The present gate-first gate-dielectric-last scheme combines the advantages of the process and design simplicity of the gate-first approach and the control of the effective gate workfunction and the interfacial oxide of the gate-dielectric-last approach. Electrical characterization data and cross-sectional images are provided as evidence of the concept.

Numerical Electron Mobility Model of Nanoscale Symmetric, Asymmetric and Independent Double-Gate MOSFETs

Numerical Electron Mobility Model of Nanoscale Symmetric, Asymmetric and Independent Double-Gate MOSFETs

Junctionless CMOS Transistors with Independent DoubleGates

Scaling is getting challenging with every technology node. Implant process requirements for defining conformal junctions in 3D device are very stringent. In addition, defining gate over topography is limited by lithography. Our solution to these problems is a novel junction-less FiNFET like transistor. Unlike conventional FiNFET the gate definition in this device is lithography independent. The fabricated NMOS and PMOS shows good transistor characteristics: I ON =52.3 uA/um, ION/IOFF ratio = 10 7 , SS = 92mV/dec for NMOS and ION =15.4 uA/um, ION/IOFF ratio = 10 5 , SS = 90mV/dec for PMOS. We also show inverter VTC characteristics fabricated using this NMOS and PMOS.

Independent-Double-Gate FinFET SRAM Technology

Independent-double-gate (IDG) FinFET SRAM technology has been developed. V th controllable IDG-FinFET technology enables noise margin enhancement of SRAM cells. The IDG-FinFET is also effective for the reduction of variation effect due to the work function variation (WFV) of the TiN metal-gate.

BSIM—SPICE Models Enable FinFET and UTB IC Designs

Two turn-key surface potential-based compact models are developed to simulate multigate transistors for integrated circuit (IC) designs. The BSIM-CMG (common-multigate) model is developed to simulate double-, triple-, and all-around-gate FinFETs and it is selected as the world's first industry-standard compact model for the FinFET. The BSIM-IMG (independent-multigate) model is developed for independent double-gate, ultrathin body (UTB) transistors, capturing the dynamic threshold voltage adjustment with back gate bias. Starting from long-channel devices, the basic models are first obtained using a Poisson-carrier transport approach. The basic models agree with the results of numerical two-dimensional device simulators. The real-device effects then augment the basic models. All the important real-device effects, such as short-channel effects (SCEs), quantum mechanical confinement effects, mobility degradation, and parasitics are included in the models. BSIM-CMG and BSIM-IMG have been validated with hardware silicon-based data from multiple technologies. The developed models also meet the stringent quality assurance tests expected of production level models.

Soft error study in double gated FinFET-based SRAM cells with simultaneous and independent driven gates

Common double gate-FinFET (simultaneously driven gates) and independent double gate-FinFET (independently driven gates) based 6T-SRAM cells are studied in this paper for their Single Event Upset (SEU) or soft error performance using 3D TCAD simulations. Four different topologies, one common double gate-FinFET-based topology and three independent double gate-FinFET-based topologies namely, Flex-VTH, Flex-PG, and PG-SN are studied to find out their minimum radiation dose required to flip SRAM cell. The simulation results reveal that the independent double gate FinFETs in place of access devices in 6T-SRAM does not degrade the soft error performance significantly whereas the independent gate devices inside the cell, in the inverters, degrades the performance significantly.

TCAD Simulation of Digital Logic Gates in Independent Double Gate Transistors – A Comparative Study between Conventional and Junctionless FETs

In this work, conventional independent double gate structure and Junctionless independent double gate structure-based inverters and NAND gates are studied and compared using TCAD simulation. The Junctionless device- based circuits show a larger delay with smaller dynamic power whereas the conventional device-based circuits show smaller delay with larger dynamic power which is a simple power-delay trade-off.

Poly-Si Nanowire Device Technology

In this article we review the progress made in poly-Si nanowire (NW) transistor technology in recent years, with major attention paid on several device structures developed by our group. With these NW structures, superior device characteristics over the previous planar structures have been demonstrated. A common feature of fabricating these structures is that the formation of poly-Si NW can be accomplished with simple process techniques without involving advanced lithography tools and processes, such as e-beam or DUV. One important implication of this feature is that these NW structures can be readily integrated with modern poly-Si TFT-based electronics on the same panel or CMOS circuitry. This can increase the functionally of a panel and chip products. Several multi-gate (MG) configurations have been developed and characterized. Moreover, these MG structures can be designed with either common or independent gate configuration. The above NW devices have been applied to bio-logic sensor and memory applications. In the former regard, the testing is usually performed in an aqueous solution. In our experiments weve found an interesting water passivation effect. Specifically, the H-related species contained in the test solution would passivate the defects presenting at the grain boundaries of the poly-Si NW, greatly enhancing the device performance. This may further lift the concern associated with the granular structure of poly-Si NW. Finally, weve also employed the NW devices as the test vehicle and have successfully demonstrated its effectiveness in detecting the pH value of the solutions, as well as the dopamine and DNA. Weve also fabricated the NW SONOS devices and showed that the use of NW can help promote the programming/erasing (P/E) speed over the planar counterparts. Moreover, the independent double-gate (DG) configuration could further help improve the P/E efficiency and provide more flexibility for read operation. These promising results indicate the great potential of the poly-Si NW devices for future 3D high-density non-volatile memory (NVM) applications.

Read Characteristics of Independent Double-Gate Poly-Si Nanowire SONOS Devices

This paper investigates the read operation of poly-Si nanowire silicon-oxide-nitride-oxide-silicon devices with independent double-gate (IDG) configuration. The device features oxide-nitride-oxide (ONO) stack as the charge storage medium in one of the two gated sides with pure oxide in the other. Owing to the IDG feature, the shift in the device's transfer characteristics due to a change in the amount of storage charges can be sensed with two different modes, which have one of the two gates applied with a sweeping bias (driving gate) and the other with a fixed bias (control gate). Our analysis and experimental data show that a larger memory window is obtained when the gate of the ONO side is used as the driving gate. Moreover, the memory window of this mode is essentially independent of the bias applied to the control gate. Based on this finding, a novel Flash structure featuring IDG cells with a common control gate is proposed.