Reduced interfacial fluctuation leading enhanced mobility in a monolayer MoS2 DG FET under low vertical electric field

Abstract

Compared to the silicon device whose performance is severely degraded due to the pin-holes and channel inactive space when the channel thickness is less than 1 nm, despite monolayer transition-metal dichalcogenides being the most stable structure to be used as a two-dimensional semiconductor material, precise analysis of the double-gate (DG) field-effect transistor (FET) device structure has hardly been performed thus far. Hence, we analyzed the device operation characteristics of single-gate and DG sweeps in a monolayer MoS2 DG FET structure, where the interfacial carrier behavior is distinguished from both gates by the different gate dielectric materials at the top and bottom. The synchronized DG sweep operation with biasing of VTG and VBG (=10 VTG) increased the carrier mobility by a factor of 4.85 compared with the independent DG sweep. Direct-current analysis and low-frequency noise modeling indicate that the device performance improves under equivalent gate voltages from both sides, because the device operates in a low vertical electric field and the interfacial carrier fluctuation effect is significantly reduced.