Increasing Gate Voltage Research Articles

Controllable p‐to‐n Type Conductance Transition in Top‐Gated Graphene Field Effect Transistor by Interface Trap Engineering

AbstractModulating the electronic property of graphene by doping is essential for its device and circuit applications. Unfortunately, controllable p‐ and n‐type doping in top‐gated graphene field effect transistor (GFET) is reported. Here, the O3‐based atomic layer deposited Al2O3 layer as top gate dielectric is chosen. The epoxide functional group formed in the O3 process serves as effective interface trap sites. As the sweeping range of top gate voltage increases, the Dirac point position of GFET moves from positive voltage to negative voltage. The shift of the Dirac point voltage indicates the doping transition of graphene from p‐type to n‐type. The gate voltage dependent doping can be attributed to the charge exchange between graphene and interface trap sites. Furthermore, a trap‐dependent charge model is proposed to explain the transport mechanism in the doping process. This approach is promising to produce the complementary p‐ and n‐type top‐gated GFET for multiple applications.

Universal Bacterial Detection Utilizing PEDOT:PSS-Based Organic Electrochemical Transistors

Bacteria are one of the most common sources of illness, responsible for a wide range of infections. Bacterial infections can be caused from a variety of sources, with thousands of deaths attributed to waterborne outbreaks alone [1]. Detection of both infectious and non-infectious bacteria is utilized to ensure commercial goods and water are safe for consumers. Current detection of bacterial contamination typically uses cell culture plates to measure the number of colony forming bacteria (CFU/ml) in a liquid media. This technique is widely used due to its high sensitivity and easy visual readout. Unfortunately, culture counting techniques is time consuming (1-3 days), requires skilled lab technicians, can be contaminated during preparation, and cannot be integrated into the desired testing media directly.To overcome these limitations, many bacterial sensors and detection techniques have been developed over the last few decades [2]. A recent sensor for bacteria detection is the organic electrochemical transistor (OECT). OECTs are polymer-based transistors that utilize ionic solutions to de-dope and re-dope a conducting channel. These devices are known for their high transconductance, bio-compatibility, low operating voltage, low cost, small size, ease of integration into measurement systems, and ability to function in aqueous environments [3]. Detection of a single bacteria is typically desired and achieved through the capture of bacteria cells onto the OECT channel area [4]. This approach allows for rapid detection of a specific pathogen with high sensitivity. However, for detecting contamination from a variety of bacteria a different approach must be used.We have investigated the OECT response to the presence of non-captured bacteria present within the OECT operating media. In this approach cells are detected both in solution and on the surface of the source-drain channel and on the gate electrode. Presence of bacteria between the gate and channel region will cause an increase in effective gate voltage, resulting in a decrease in source-drain current. Detection and characterization of (non-bacteria) whole cells has previously been reported utilizing this approach [5, 6]. In our work we have focused on the bacteria pseudomonas fluorescens (p. fluorescens) due to its size (~1µm) and potential as a water borne pathogen. P. fluorescens was cultured in LB media, diluted to three different concentrations, and used as the operating media for OECT. Concentrations of 8.7e12, 8.7e11, and 8.7e10 CFU/ml were found to shift source-drain current by 16.1, 13.8, and 12.3µA, respectively. From this data a present lower limit of detection for the sensor is estimated to be ~5.0e4 CFU/ml. 1. Craun, G.F., Statistics of waterborne outbreaks in the US (1920–1980). Waterborne diseases in the United States, 2018: p. 73-159.2. Ahmed, A., et al., Biosensors for whole-cell bacterial detection. Clinical microbiology reviews, 2014. 27(3): p. 631-646.3. Strakosas, X., M. Bongo, and R.M. Owens, The organic electrochemical transistor for biological applications. Journal of Applied Polymer Science, 2015. 132(15).4. Demuru, S., et al. Flexible Organic Electrochemical Transistor with Functionalized Inkjet-Printed Gold Gate for Bacteria Sensing. in 2019 20th International Conference on Solid-State Sensors, Actuators and Microsystems & Eurosensors XXXIII (TRANSDUCERS & EUROSENSORS XXXIII). 2019. IEEE.5. Liao, J., et al., Organic electrochemical transistor based biosensor for detecting marine diatoms in seawater medium. Sensors and Actuators B: Chemical, 2014. 203: p. 677-682.6. Ramuz, M., et al., Monitoring of cell layer coverage and differentiation with the organic electrochemical transistor. Journal of Materials Chemistry B, 2015. 3(29): p. 5971-5977. Figure 1

Bound Electron Pairs Formed by the Spin–Orbit Interaction in 2D Gated Structures

The bound electron pairs (BEPs) arising due to the pair spin–orbit interaction (PSOI) in 2D structures are explored with a gate that allows the BEPs to be manipulated. The gate breaks the in‐plane reflection symmetry of the pair Coulomb field and creates a one‐particle Rashba spin–orbit interaction. It is found that the normal component of the electric field substantially affects the BEPs but the key role in forming the BEPs belongs to the in‐plane component. The ground state of a BEP with zero total momentum, which is doubly degenerate in the absence of the gate, splits into two states. One of them is tunable by varying the gate voltage, whereas the other is on the contrary robust. The tunable BEP has a higher binding energy which grows as the gate voltage increases, with its orbital and spin structure changing continuously. At large negative voltage, the tunable BEP decays. The orbital and spin structure of the robust BEP does not depend on the gate voltage. Its energy level crosses the conduction band bottom at high gate voltage of any polarity, but the robust BEP remains bound and localized even when in continuum.

Characteristics of hydrogen-terminated single crystalline diamond field effect transistors with different surface orientations

Diamond has great potential applications in high-power, high-frequency semiconductor devices because of its wide band gap (5.5 eV), high thermal conductivity (22W/(cm·K)), and high carrier mobility (4500 cm<sup>2</sup>/(V·s) for electron, and 3800 cm<sup>2</sup>/(V·s) for hole). It has been widely considered as an ultimate semiconductor. From the analysis of our previous work, we find that the output current of field effect transistor based on hydrogen-terminated polycrystalline diamond is usually larger than that based on single crystal diamond, and that the preferential orientations of the polycrystalline diamond are mainly <inline-formula><tex-math id="Z-20200108113531-1">\begin{document}$ \langle 110\rangle $\end{document}</tex-math><alternatives><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="2-20191013_Z-20200108113531-1.jpg"/><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="2-20191013_Z-20200108113531-1.png"/></alternatives></inline-formula> and <inline-formula><tex-math id="Z-20200108113531-2">\begin{document}$ \langle 111\rangle $\end{document}</tex-math><alternatives><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="2-20191013_Z-20200108113531-2.jpg"/><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="2-20191013_Z-20200108113531-2.png"/></alternatives></inline-formula> shown by XRD results. Therefore, in order to further analyze the effect of surface orientation on the device performance of hydrogen-terminated diamond field effect transistor (FET), we study the devices fabricated respectively on the (110) plane and (111) plane single crystal diamond plates obtained from a single 3.5-mm-thick single crystal diamond grown by the microwave plasma chemical vapor deposition on the high-pressure high-temperature synthesized diamond substrate. Prior to processing the device, these diamond plates are characterized by atomic force microscope, Raman spectra and photoluminescence (PL) spectra. The results of Raman and PL spectra show that (110) plane and (111) plane plates originating from the same CVD single crystal diamond have no significant difference in optical property. Then the normally-on hydrogen-terminated diamond FET with a gate length of 6 μm is achieved. The device on (111) plane delivers a saturation drain current of 80.41 mA/mm at a gate voltage <i>V</i><sub>GS</sub> = –4 V, which is approximately 1.4 times that of the device on (110) plane. Meanwhile, the on-resistance of the device on (111) plane is 48.51 Ω·mm, and it is only 67% of the device on (110) plane. Analyses of the capacitance-voltage show that the hole concentration of the gated device on (110) plane and (111) plane are 1.34 × 10<sup>13</sup> cm<sup>–2</sup> and 1.45 × 10<sup>13</sup> cm<sup>–2</sup>, respectively, approximately at the same level. In addition, the hole density of the device on both (110) and (111) plane increase near-linearly with the increase of gate voltage from the threshold voltage to – 4 V, indicating that the control effect of the gate on the carrier in the channel is uniform. The possible reason for the higher saturation drain current as well as the lower on-resistance of the device on (111) plane is that its sheet resistance is lower.

Random telegraph noise in gate-all-around silicon nanowire MOSFETs induced by a single charge trap or random interface traps

The random telegraph noise (RTN) in gate-all-around (GAA) silicon (Si) nanowire (NW) metal–oxide–semiconductor field-effect transistors (MOSFETs) induced by a single charge trap (SCT) or random interface traps (RITs) is studied for the first time. An experimentally validated three-dimensional quantum-mechanically-corrected device simulation is advanced to investigate the explored devices. The magnitude of the RTN decreases with increasing gate voltage to different extents for the planar MOSFET, bulk FinFET, and GAA Si NW MOSFET devices, owing to the reduction in the conducting carriers along the channel. For the GAA Si NW MOSFET, the reduction of the fluctuation of threshold voltage in the presence of RITs is about 25 and 3 times when compared with the planar MOSFET and bulk FinFET device, respectively, whereas this reduction in the presence of an SCT is about 6 and 2.6 times, respectively. For the GAA Si NW MOSFET, the reduction of the RTN in the presence of RITs is about 7.5 and 4.7 times when compared with the planar MOSFET and bulk FinFET device, respectively, whereas this reduction in the presence of an SCT is about 22 and 6 times, respectively. At given threshold voltage, compared with the results for the planar MOSFETs and bulk FinFET, the GAA Si NW MOSFET exhibits minimal characteristic variability and RTN owing to the ultimate electrostatic control of the gate from the point of view of electrostatic integrity.

Hot carrier instability associated with hot carrier injection and charge injection in In0.7Ga0.3As MOSFETs with high-κ stacks

Channel hot carrier (CHC) reliability in In0.7Ga0.3As nMOSFETs with Al2O3/HfO2 (EOT = 0.8 nm) during CHC stress has been studied in scaled-down gate devices. The threshold voltage degradation (ΔVT) during CHC stress was attributed to the hot carrier injection into Al2O3 or/and HfO2 defect sites, rather than charge trapping into high-κ bulk defects. Additionally, with an increase of gate voltage at a fixed drain voltage (VDS), there was an increase in probability that the InGaAs channel carriers are easily injected into Al2O3 or/and HfO2 defect sites, causing the worst ΔVT degradation at the same VGS = VDS stress condition. Hence, hot carrier injection during CHC stress was divided into two components: charge injection by the vertical field near the source region and injection of hot carriers into the oxide bulk defects at the drain corner. To decouple the charge trapping and hot carrier injection into the gate oxide defect sites during CHC stress, an unrecovered (hot carrier damage) and recovery ratio (charge injection) of the ΔVT degradation after relaxation and opposite polarity voltage were calculated to be about ∼70% and ∼30%, respectively. Therefore, hot carrier injection has emerged as a dominant degradation factor in InGaAs MOSFETs with high-κ dielectrics.

Anomalous Broadband Spectrum Photodetection in 2D Rhenium Disulfide Transistor

Abstract2D transition metal dichalcogenide (TMD)‐based phototransistors generally work under photoconductive, photovoltaic, or photogating mode, in which photocarriers are generated from band‐to‐band excitation. Nevertheless, due to the relatively large bandgap, most TMD phototransistors working under these modes are restricted in visible spectrum. Here, photodetection in 2D multilayer rhenium disulfide (ReS2) transistor via bolometric mode, which relies on light heating induced conductance change instead of band‐to‐band photoexcitation is reported, making it possible for sub‐bandgap photon detection. The bolometric effect induced photoresponse is first revealed by an anomalous sign switching of photocurrent from positive to negative while increasing gate voltage under visible light, which is further validated by the temperature dependent electrical transport measurements. The phototransistor exhibits remarkable photoresponse under infrared regime, beyond the optical bandgap absorption edge of the ReS2 flake. Additionally, it demonstrates a low noise equivalent power, less than 5 × 10−2 pW Hz−1/2, which is very promising for ultra‐weak light detection. Moreover, the response time is below 3 ms, nearly 3–4 orders of magnitude faster than previously reported ReS2 photodetectors. The findings promise bolometric effect as an effective photodetection mode to extend the response spectrum of large bandgap TMDs for novel and high‐performance broadband photodetectors.

Modeling of Ballistic Monolayer Black Phosphorus MOSFETs

In this paper, we present two accurate physics-based models of ballistic metal–oxide–semiconductor field-effect transistors (MOSFETs), both using less than ten parameters. These models—the capacitor model and the virtual source model—are based on the Landauer–Buttiker formalism. We show that the nonthermalization of charge carriers in the channels of ballistic MOSFETs leads to two critical effects that need to be considered in the modeling: the ballistic drain-induced barrier lowering (DIBL) effect and the floating source effect. The ballistic DIBL effect is responsible for a drain voltage dependence of the DIBL parameter; the floating source effect intensifies the injection of high-energy carriers from the source as the gate voltage increases. Specifically, the analysis is carried out on devices composed of monolayer black phosphorus, a 2-D semiconductor with unique electronic and mechanical properties, which make it a promising candidate for 2-D digital logic applications.

Characterization of Deep and Shallow Traps in GaN HEMT Using Multi-Frequency C-V Measurement and Pulse-Mode Voltage Stress

In this paper, the influence of interface traps at the SiN/GaN interface and carbon-related buffer traps on GaN high electron mobility transistor (HEMT) on silicon substrate has been studied using high-frequency capacitance-voltage (HFCV) and quasi-static C-V (QSCV) measurement. The correlation between dynamic resistance degradation and trap density distribution subjected to pulse stress conditions has been examined. Deeper-level traps from the hole-emission process of the carbon-related buffer layer are activated by high drain voltage during off-state stress, and shallow-level traps at the SiN interface are enhanced by an increase in gate voltage during the on-state stress. 2-D device simulations have been carried out to probe the physical insight into the dynamic resistance degradation. Good agreement between experimental data and simulated results is obtained while taking into account shallow-level and deeper-level traps.

A study of variable range hopping conduction of a sol-gel ZnSnO thin film transistor using low temperature measurements

This paper investigates variable range hopping conduction of a zinc tin oxide (ZTO) thin-film transistor (TFT). The ZTO channel layer was fabricated using a sol-gel process. Existence of Zn2SnO4 and ZnSnO3 crystal phases in the ZTO film is observed in the X-ray diffraction pattern. Distinct lattice fringes with different orientations that are observed in the transmission electron microscopy image verify the polycrystalline structure of the ZTO layer. To study the hopping mechanism, electrical characteristics of the ZTO TFT were measured at low temperatures of 100–220 K. The activation energy (Ea) is 97 meV when the gate voltage is 0 V, and it exponentially decreases with increasing gate voltage. The Ea is 22 meV when the gate voltage increases to 30 V. A negative exponential relationship between the density of states and the Ea is found. Temperature and gate voltage dependence of the hopping distance and hopping energy are also explored.

Gate-tunable large spin polarization in a few-layer black phosphorus-based spintronic device.

We report a first principles study of the gate tunable spin transport properties in trilayer black phosphorus (BP) placed on a Ni(100) electrode. In the proposed spintronic device, the spin-dependent conductance and the corresponding spin polarization can be largely modulated by the gate voltage. Instead of resorting to the gate tunable spin orbital interaction (SOI) mechanism in the traditional spintronic devices, the control scheme here is achieved by the giant Stark effect induced semiconducting-metallic phase transition of the few-layer BP. It is found that the quantum tunneling effect is gradually reduced as the gate voltage increases. During this process, the conductances of spin up and spin down components increase differently and hence the spin polarization is largely varied from 7% to 77% in parallel configuration (PC) and from 1% to 54% in anti-parallel configuration (APC). More importantly, the maximum magnetoresistance (MR) value can reach as large as 80%. Finally, we find that the non-equilibrium spin-polarized current can also be controlled by the external bias voltage. For instance, a large turn on/off ratio can be realized by the gate voltage (4239 for spin down current and 1809 for spin up current) when the bias voltage is fixed at 0.01 V. Our theoretical findings pave a feasible way for the novel application of few-layer BP in spintronic nanodevices.

Light-enhanced gating effect on the persistent photoconductivity at LaAlO<sub>3</sub>/SrTiO<sub>3</sub> interface

The LaAlO<sub>3</sub>/SrTiO<sub>3</sub> interface has been one of the topics studied most during the past few years due to its many intriguing properties such as the two-dimensional electron gas, transient photoconductivity (PC), persistent photoconductivity (PPC), and the coexistence of the PC and PPC. Of them, the PPC effect is the most interesting because of its potential application in exploring the photoelectric memory devices. Until now, tuning of the PPC of the LaAlO<sub>3</sub>/SrTiO<sub>3</sub> interface under the external stimuli, such as electric or magnetic field is less addressed, while the relevant knowledge is of great value for exploring the memory devices with multifunctionality. In this paper, we report on an electric field control of the persistent PPC at the LaAlO<sub>3</sub>/SrTiO<sub>3</sub> interface. Our LaAlO<sub>3</sub>/SrTiO<sub>3</sub> heterojunction is fabricated by growing the LaAlO<sub>3</sub> film on the SrTiO<sub>3</sub> substrates through using pulsed laser deposition. The substrate temperature is kept at 750 ℃ and the partial pressure of oxygen is maintained at 3.3 × 10<sup>–5</sup> Torr (1 Torr = 1.33322 × 10<sup>2</sup> Pa) during the deposition. The thickness of LaAlO<sub>3</sub> film is controlled to be about 2 nm by setting an appropriate deposition time. The X-ray diffraction experiment confirms that the LAO film is well epitaxial and of single phase. To guarantee the good electric contacts, Al electrodes are soldered at the LaAlO<sub>3</sub>/SrTiO<sub>3</sub> interface and the back side of the SrTiO<sub>3</sub> respectively by ultrasonic welding. We find that the PPC at the LaAlO<sub>3</sub>/SrTiO<sub>3</sub> interface can be significantly reinforced and modulated by the light-enhanced gating effects: that is, after a negative back gate voltage processing combined with a simultaneous light illumination, the LaAlO<sub>3</sub>/SrTiO<sub>3</sub> interface can exhibit a notable PPC effect. And the PPC effect increases as the negative gate voltage increases, and then attains a maximum at a back gate voltage of about –70 V. Further increase of the negative gate voltage can cause the PPC to decrease. Additionally, the PPC is also found to increase monotonically with increasing the gating time. The present result can be understood in terms of the migration of the oxygen vacancies under the influence of photoelectric synergetic effect. This field enhanced PPC effects at the LaAlO<sub>3</sub>/SrTiO<sub>3</sub> interface may find their applications in designing the photoelectric memory devices with electric tunability.

Probing the optical characteristics of MoS2 under external electrical fields using polarized Raman spectroscopy

Raman spectroscopy effectively revealed a strain-induced electronic structure change during polarization-dependent studies on molybdenum disulfide (MoS2). Initially, we used a polarized Raman system to obtain the polarization-dependent Raman spectra of single-, bi-, and tri-layer MoS2 and analyzed their vibration modes. We determined that the in-plane () mode of vibration was double-degenerate whereas the out-of-plane (A1g) mode of vibration was not. We also observed the mode to be independent of polarization, and the A1g mode to be quadratically dependent on the cosine of the polarization angle. The experimental data agreed strongly with the theoretical models. We present the Raman spectra collected with applied top gate voltages and operational frequencies for an MoS2 transistor. The Raman signal intensities, peak positions, and linewidths of two active modes were calculated under different applied top gate voltages and operational frequencies. The broadening of linewidth for the out-of-plane mode was a result of the strengthening of electron–phonon coupling with increasing gate voltage. Owing to the electric potential across the metal-MoS2 interface, a dramatic frequency shift can be observed. For the AC operational mode, the Raman signals can be regarded as constant in the proper operational frequency region.

Polarization Engineering in PZT/AlGaN/GaN High-Electron-Mobility Transistors

Polarization engineering in 30-nm Pb (Zr,Ti) O3 (PZT)/AlGaN/GaN high-electron-mobility transistors (HEMTs) is demonstrated. The coupling between ferroelectric polarization and 2-D electron gas (2DEG) showed a remarkable increase in transconductance during the down-sweep process; this can be attributed to the switching of ferroelectric polarization. With the increase in maximum gate voltage, the transfer curve showed a positive shift; this is because of the increase in polarization charges induced by gate voltage. The drain electric field affected the polarization of ferroelectric layer, leading to different hysteresis behaviors and peak transconductance trends of transfer curves. To decrease the effect of drain electric field on gate, a small drain voltage was used to evaluate the characteristics of PZT/AlGaN/GaN. The variation in peak transconductance was used to estimate the recovery and pinning degree of polarization. The ferroelectric layer modulates the 2DEG in ferroelectric/AlGaN/GaN HEMTs; this mechanism provides guidelines for designing and electrically controlling ferroelectric/AlGaN/GaN HEMTs.

A vertical WSe2-MoSe2 p-n heterostructure with tunable gate rectification.

Here, we report the synthesis of a vertical MoSe2/WSe2 p–n heterostructure using a sputtering-CVD method. Unlike the conventional CVD method, this method produced a continuous MoSe2/WSe2 p–n heterostructure. WSe2 and MoSe2 back-gated field effect transistors (FETs) exhibited good gate modulation behavior, and high hole and electron mobilities of ∼2.2 and ∼15.1 cm2 V−1 s−1, respectively. The fabricated vertical MoSe2/WSe2 p–n diode showed rectifying I–V behavior with back-gate tunability. The rectification ratio of the diode was increased with increasing gate voltage, and was increased from ∼18 to ∼1600 as the gate bias increased from −40 V to +40 V. This is attributed to the fact that the barrier height between p-WSe2 and n-MoSe2 is modulated due to the back-gate bias. The rectification ratio is higher than the previously reported values for the TMDC p–n heterostructure grown by CVD.

Analytical model of hot carrier degradation in uniaxial strained triple-gate FinFET for circuit simulation

The triple-gate (TG) SOI FinFET has well suppressed short-channel effects compared to planar MOSFET due to increased gate voltage controllability. However, the hot carrier injection (HCI) is a serious reliability issue for nanoscale FinFET and this should be taken care for reliable circuit design. The introduction of uniaxial strain in the channel of FinFET to enhance the performance further limits the reliable design of VLSI circuits. Hence, there is a great need to capture these device-level variations in circuits through physics-based models. In this paper, one such analytical model of hot carrier (HC) degradation in uniaxial strained TG FinFET based on reaction–diffusion mechanism is developed, considering various geometrical aspects of the device, for the first time. The developed model is validated using experimentally calibrated Sentaurus TCAD simulation results. The results show that the strain in the channel worsens the degradation of threshold voltage due to HCI. The developed model is integrated in Cadence circuit simulator, and the impact of HC degradation in strained TG FinFET-based CMOS NAND logic circuit is analyzed.

Design and Simulation of a Novel Graded-Channel Heterojunction Tunnel FET With High ${I} _{\scriptscriptstyle\text {ON}}/{I} _{\scriptscriptstyle\text {OFF}}$ Ratio and Steep Swing

In this letter, a novel graded-channel heterojunction tunnel field-effect transistor (GCH-TFET) is proposed and studied by simulation. The novel TFET adopts a near broken-gap heterojunction at the source/channel interface to enhance the tunnel efficiency. Besides, it employs a graded component channel which works as an electron barrier to block up the leakage current at the OFF-state and can be removed with the increased gate voltage at the ON-state for high ON/OFF-current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ) ratio. Such graded channel also allows a sudden turn-on of band-to-band tunneling, resulting in a reduced sub-threshold swing (SS) compared with conventional heterojunction TFETs. The GCH-TFET demonstrates an I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio of more than seven decades with I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> up to 225 μA/μm at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 0.3 V, I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> more than two decades lower than a near broken-gap heterojunction TFET and SS lower than 30 mV/decade for more than five decades, exhibiting excellent potential for ultra-low power applications.

Characterization of Few layer Tungsten diselenide based FET under Thermal Excitation

Abstract:Two-dimensional (2D) materials are very promising with respect to their integration into optoelectronic devices. Monolayer tungsten diselenide (WSe2) is a direct-gap semiconductor with a bandgap of ∼1.6eV, and is therefore a complement to other two-dimensional materials such as graphene, a gapless semimetal, and boron nitride, an insulator. The direct bandgap distinguishes monolayer WSe2 from its bulk and bilayer counterparts, which are both indirect gap materials with smaller bandgaps. This sizable direct bandgap in a two-dimensional layered material enables a host of new optical and electronic devices. In this work, a comprehensive analysis of the effect of optical excitation on the transport properties in few-layer WSe2 is studied. Monolayer WSe2 flakes from natural WSe2 crystals were transferred onto Si/SiO2 (270nm) substrates by mechanical exfoliation. The flakes were observed under an optical microscope. A FET based on mechanically exfoliated WSe2 was fabricated using photolithography with Molybdenum as metal contact and Silicon as back gate and the electronic properties were measured in a wide range of temperatures. The mobility of our device was found to be 0.2 cm /V-S at room temperature. The schottky barrier height was found to decrease from 80 meV to 25 meV as the gate voltage increases.

Abrupt disappearance and re-emergence of the SU(4) and SU(2) Kondo effects due to population inversion

The interplay of almost degenerate levels in quantum dots and molecular junctions with possibly different couplings to the reservoirs has lead to many observable phenomena, such as the Fano effect, transmission phase slips and the SU(4) Kondo effect. Here we predict a dramatic repeated disappearance and reemergence of the SU(4) and anomalous SU(2) Kondo effects with increasing gate voltage. This phenomenon is attributed to the level occupation switching which has been previously invoked to explain the universal transmission phase slips in the conductance through a quantum dot. We use analytical arguments and numerical renormalization group calculations to explain the observations and discuss their experimental relevance and dependence on the physical parameters.

Weak localization in electric-double-layer gated few-layer graphene

We induce surface carrier densities up to ∼ cm−2 in few-layer graphene devices by electric double layer gating with a polymeric electrolyte. In 3-, 4- and 5-layer graphene below 20–30 K we observe a logarithmic upturn of resistance that we attribute to weak localization in the diffusive regime. By studying this effect as a function of carrier density and with ab initio calculations we derive the dependence of transport, intervalley and phase coherence scattering lifetimes on total carrier density. We find that electron–electron scattering in the Nyquist regime is the main source of dephasing at temperatures lower than 30 K in the ∼1013 cm−2 to ∼ cm−2 range of carrier densities. With the increase of gate voltage, transport elastic scattering is dominated by the competing effects due to the increase in both carrier density and charged scattering centers at the surface. We also tune our devices into a crossover regime between weak and strong localization, indicating that simultaneous tunability of both carrier and defect density at the surface of electric double layer gated materials is possible.