Increasing Channel Doping Research Articles

Assessing the analog/RF and linearity performances of FinFET using high threshold voltage techniques

One of the severe issues of the downscaling of semiconductor devices is the threshold voltage reduction which significantly increases the leakage current. Thus, high threshold voltage (HVT) techniques are required to bring down the leakage hike for improved performances. In this paper, for the first time, we investigate the analog/radio frequency (RF) and linearity performances of silicon (Si) FinFET by employing HVT techniques. Using well-calibrated technology computer aided design models, to mitigate the leakage current, we analyzed the following approach to get HVT: (a) increasing channel doping (N ch′); (b) making drain-side underlap (L dsu); (c) increasing gate length (L g′). Two flavors of fin field effect transistors (FinFETs) viz bulk and silicon-on-insulator (SOI) are suitably compared over their baseline counterpart, i.e. without HVTs. A thorough investigation of analog/RF metrics such as transconductance, output resistance, gate capacitance, cut-off frequency, gain-bandwidth, and transconductance-frequency product proves the eminence of bulk-FinFET over its peer SOI-FinFET. In contrast, SOI-FinFET shows merits in intrinsic gain and linearity such as g m2, g m3, VIP2, VIP3, IIP3, IMD3, and 1 dB compression point. Thus, HVT techniques are worth analyzing for a FinFET architecture employed in analog/RF applications.

SEB Hardened Power MOSFETs With High-K Dielectrics

Simulations of the SEB hardness of power MOSFETs are carried out with an experimentally calibrated structure. The effects of incorporating high permittivity gate dielectric layers and increasing channel doping concentration are investigated. The simulation results indicate that high-k dielectrics and high channel doping are promising methods to achieve SEB-hardened power MOSFETs. This offers a potential path to power MOSFETs that are resistant to SEB with thinner, more radiation-tolerant gate dielectrics.

Comparative Leakage Analysis of GeOI FinFET and Ge Bulk FinFET

We present a comparative leakage analysis of germanium-on-insulator (GeOI) FinFET and germanium on bulk substrate FinFET (Ge bulk FinFET) at device and circuit levels. Band-to-band tunneling (BTBT) leakage-induced bipolar effect is found to result in an amplified BTBT leakage for GeOI FinFET. Device and circuit designs to mitigate the amplified BTBT leakage of GeOI FinFETs are suggested. The effectiveness of various high threshold voltage technology options including increasing channel doping, increasing gate length and drain-side underlap for leakage reduction is analyzed.

A Closed-Form Quantum “Dark Space” Model for Predicting the Electrostatic Integrity of Germanium MOSFETs With High-$k$ Gate Dielectric

This paper provides a closed-form model of the “dark space (DS)” for Ge MOSFETs with high- k gate dielectrics. This model shows accurate dependences on barrier height, surface electric field, and quantization effective mass of the channel and gate dielectric. Our model predicts that the surface DS due to quantum confinement decreases with reverse substrate bias and increasing channel doping. Our model can be also used for devices with a steep retrograde doping profile. This physically accurate model will be crucial to the prediction of the subthreshold swing and electrostatic integrity of advanced Ge devices.

Analysis of 1.2 kV SiC buried-grid VJFETs

1.2 kV buried-grid vertical 4H-SiC JFET structures with normally-on (N-on) and normally-off (N-off) designs were investigated by simulation. The static and dynamic characteristics of the devices were determined over a wide range of current, voltage and gate drive conditions in the temperature range −50 °C to 250 °C. In this paper, the properties of the N-on designs with threshold voltages (Vth) −50 and −10 V are compared with the properties of the N-off design (Vth=0). For constant Vth, on-resistance decreases and output current increases with increasing channel doping and decreasing channel width. Simulations show that an on-resistance lower than 2 mΩ cm2 at 250 °C can be obtained provided the channel width is smaller than 1.5 and 0.5 μm for N-on JFETs with Vth=−50 V and Vth=−10 V, respectively, and lower than 3 mΩ cm2 provided the channel width is smaller than 0.3 μm for the N-off JFET. At the same time, Eon decreases and Eoff increases with increased channel doping concentration and reduced channel width. It is shown that Eon decreases with increasing channel doping concentration due to the reduced channel resistance for the faster turn-on process. Eoff increases with increasing channel doping concentration due to the increase in gate–drain capacitance, CGD.

Feasibility of Efficient Power Switching Using Short-Channel 1200-V Normally-Off SiC VJFETs; Experimental Analysis and Simulations

A recessed implanted-gate short-channel 1290-V normally-OFF 4H-SiC vertical-channel JFET (VJFET), fabricated in seven photolithographic-levels, with a single masked ion-implantation and no epitaxial regrowth, is evaluated for efficient power conditioning. Under unipolar high-current-gain operation, which is required for efficient power switching, the 1200-V N-OFF (enhancement mode) VJFET exhibits prohibitively high on-state resistance. Comparison with 1200-V normally-ON VJFETs, fabricated on the same wafer, confirms experimentally that the strong gate-depletion-region overlap required for 1200-V normally-OFF blocking is the principal contributor to the prohibitively high specific on-state resistance observed under high current-gain VJFET operation. Recessed-implanted-gate VJFET channel-region optimization simulations (assuming a single commercial implantation and no epitaxial-regrowth) revealed that although aggressively increasing channel doping lowers resistance, the corresponding reduction in source mesa-width can prohibitively limit manufacturability.

Investigation of the Suitability of 1200-V Normally-Off Recessed-Implanted-Gate SiC VJFETs for Efficient Power-Switching Applications

A recessed-implanted-gate (RIG) 1290-V normally-off (N-OFF) 4H-SiC vertical-channel JFET (VJFET), fabricated with a single masked ion implantation and no epitaxial regrowth, is evaluated for efficient power conditioning applications. The relationship between the VJFET's on-state resistance and current gain is elucidated. Under high-current-gain operation, which is required for efficient power switching, the 1200-V N-OFF (enhancement mode) VJFET exhibits a prohibitively high on-state resistance. Comparison with 1200-V normally-on VJFETs, fabricated on the same wafer, confirms experimentally that the strong gate-depletion-region overlap required for 1200-V N-OFF blocking is the principal contributor to the prohibitively high specific on-state resistance observed under high-current-gain VJFET operation. Perfecting the 1200-V edge termination structure, which can reduce the theoretical drift specific ON-state resistance from 2.2 to 1.5 mOmega ldr cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , has a negligible impact in decreasing the channel-dominated 1200-V N-OFF VJFET resistance. The RIG VJFET channel-region optimization simulations (assuming a single commercial implantation and no epitaxial regrowth) revealed that, although aggressively increasing channel doping lowers the resistance, the corresponding reduction in the source mesa width can prohibitively limit manufacturability.

Optimization of n+ self-aligned short-channel normally-off GaAs MESFETs by two-dimensional numerical device simulation

The behaviour of n + self-aligned short-channel normally-off GaAs MESFETs with increasing channel doping concentration is investigated by detailed computer simulation. Characteristic data of n + self-aligned technology like n +-gate spacing and projected range of n +-implant are optimized. For the calculation a two-dimensional numerical GaAs device simulation program developed at Dresden University of Technology is used. Increasing channel doping concentration up to 10 18 cm −3 decreases sensitivity of threshold voltage upon gate length by about 25–30%. Furthermore, transconductance and K-value are increased by more than twofold. A transconductance of 610 mS/mm was calculated for a GaAs normally-off MESFET with 0.5 μm gate. This is a remarkably high value for MESFETs.

Hot-hole-induced degradation in depletion-mode n -channel MOSFETs

Injection and trapping of hot holes was studied in n-channel depletion-mode MOSFETs and compared to that in enhancement devices. The rate of device degradation was found to decrease with increasing channel doping. A model is proposed explaining this behaviour from the current transport in the buried channel and from the effect of the channel doping level on the field near the drain.