Abstract
A recessed implanted-gate short-channel 1290-V normally-OFF 4H-SiC vertical-channel JFET (VJFET), fabricated in seven photolithographic-levels, with a single masked ion-implantation and no epitaxial regrowth, is evaluated for efficient power conditioning. Under unipolar high-current-gain operation, which is required for efficient power switching, the 1200-V N-OFF (enhancement mode) VJFET exhibits prohibitively high on-state resistance. Comparison with 1200-V normally-ON VJFETs, fabricated on the same wafer, confirms experimentally that the strong gate-depletion-region overlap required for 1200-V normally-OFF blocking is the principal contributor to the prohibitively high specific on-state resistance observed under high current-gain VJFET operation. Recessed-implanted-gate VJFET channel-region optimization simulations (assuming a single commercial implantation and no epitaxial-regrowth) revealed that although aggressively increasing channel doping lowers resistance, the corresponding reduction in source mesa-width can prohibitively limit manufacturability.
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