Increasing Clock Frequency Research Articles

A compiler and runtime system for enabling data mining applications on gpus

With increasing need for accelerating data mining and scientific data analysis on large data sets, and less chance to improve processor performance by simply increasing clock frequencies, multi-core architectures and accelerators like FPGAs and GPUs have become popular. A recent development in using GPU for general computing has been the release of CUDA (Compute Unified Device Architecture) by NVIDIA. CUDA allows GPU programming with Clanguage-like features, thus easing the development of non-graphics applications on a GPU. However, several challenges still remain in programming the GPUs with CUDA, because CUDA involves explicit parallel programming and management of its complex memory hierarchy, as well as allocating device memory, moving data between CPU anddevice memory, and specification of thread grid configurations. In this paper, we offer a solution for the programmers to generate CUDA code by specifying the sequential reduction loop(s) with some information about the parameters. With program analysis and code generation, the applications are mapped to a GPU. Several additional optimizations are also performed by the middleware. We have evaluated our system using three popular data miningapplications, k-means clustering, EM clustering, and Principal Component Analysis (PCA). The speedup that each of these applications achieve over a sequential CPU version ranges between 20 and 50.

Guest Editorial: Special Issue on Multi-Core Enabled Multimedia Applications & Architectures

The trend of multi-core processor development brings a shift of paradigm in applications development. Traditionally, increasing clock frequency is one of the main dimensions for conventional processors to achieve higher performance gains. Application developers used to improve performance of their applications by just waiting for faster processor platforms. Today, increasing clock frequency has reached a point of diminishing returns—and even negative returns if power is taken into account. Multi-core processors promise a power-efficient way to increase performance and become prevalent in vendors’ solutions. However, the application or algorithm development process must be significantly changed in order to fully explore the potential of multi-core processors. The aim of this special issue is to discuss related challenges, issues, case studies, and solutions, especially focusing on multimedia-related applications, architectures, and programming environments. This special issue opens with three papers that address overall multi-core architectures, efficient on-chip interconnect between the cores, and cache and memory subsystems to support the huge amount of computation.

A Power-Aware Placement and Routing Algorithm Targeting 3D FPGAs

In current reconfigurable architectures, the interconnect structures increasingly contribute to the delay and power consumption budget. The demand for increased clock frequencies and logic availability (smaller area foot print) makes the problem even more important, leading among others to rapid elevation in power density. Three-dimensional (3D) architectures are able to alleviate this problem by accommodating a number of functional layers, each of which might be fabricated in different technology. Since power consumption is a critical challenge for implementing applications onto reconfigurable hardware, a novel power-aware placement and routing (P&R) algorithm targeting to 3D FPGAs, is introduced. The proposed algorithm achieves to redistribute the switched capacitance over identical hardware resources in a rather balanced profile, reducing among others the number of hotspot regions, the maximal values of power sources at hotspots, as well as the percentage of device area that consumes high power. For evaluation purposes, the proposed approach is realized as a new CAD tool, named 3DPRO (3D-Placement-and-Routing-Optimization), which is part of the complete framework, named 3D MEANDER. Comparing to alternative solutions, the proposed one reduces the percentage of silicon area that operates under high power by 63%, while it leads to energy savings (about 9%), with an almost negligible penalty in application's delay ranging from 1% up to 5%.

Architecture-Level Exploration of Alternative Interconnection Schemes Targeting 3D FPGAs: A Software-Supported Methodology

In current reconfigurable architectures, the interconnection structures increasingly contribute more to the delay and power consumption. The demand for increased clock frequencies and logic density (smaller area footprint) makes the problem even more important. Three-dimensional (3D) architectures are able to alleviate this problem by accommodating a number of functional layers, each of which might be fabricated in different technology. However, the benefits of such integration technology have not been sufficiently explored yet. In this paper, we propose a software-supported methodology for exploring and evaluating alternative interconnection schemes for 3D FPGAs. In order to support the proposed methodology, three new CAD tools were developed (part of the 3D MEANDER Design Framework). During our exploration, we study the impact of vertical interconnection between functional layers in a number of design parameters. More specifically, the average gains in operation frequency, power consumption, and wirelength are 35%, 32%, and 13%, respectively, compared to existing 2D FPGAs with identical logic resources. Also, we achieve higher utilization ratio for the vertical interconnections compared to existing approaches by 8% for designing 3D FPGAs, leading to cheaper and more reliable devices.

Interconnect Criticality-Driven Delay Relaxation

Due to decreasing transistor sizes and increasing clock frequency, interconnect delay is a dominant factor in achieving timing closure in deep-submicrometer designs. In field programmable gate arrays (FPGA), interconnect delay is contributed by programmable routing switches. This increases the wire delay significantly. In FPGA devices, the interconnect delay is usually more than 40% of the total delay. Techniques like wire pipelining and retiming can manage delay of timing critical wires. However, the latency of the design limits the total pipelining in the design. Therefore, new techniques are needed at synthesis stage to consider the effect of critical wires in the design. In this paper, we propose an intuitive Critical Edge Reduction (CER) algorithm, which minimizes the number of critical wires on a maximal delay- budgeting solution under fixed latency constraint. We prove that this problem is NP-hard. We provide an integer linear programming formulation of the problem and an iterative heuristic algorithm (CER). During the course of our algorithm, we introduce multiple graph problems. We give a proof of NP-hardness of one such problem, which we call max arc-cost balancing problem. In our experiments, we present an in-depth analysis of tradeoff between various maximal budgetings and critical edge minimization. We implemented our design flow using a set of MediaBench datapaths on Xilinx VirtexE FPGA devices. Using our algorithm, the Xilinx Place-and-Route tool achieved timing closure, which is, on average, 2.8 times faster than using maximum budgeting. The resulting average clock period using CER algorithm outperforms the one using the maximum budgeting by 6%. Other results show similar advantages of critical edge minimization over traditional budgeting techniques.

Resource efficiency of the GigaNetIC chip multiprocessor architecture

In this article, we present the prototypical implementation of the scalable GigaNetIC chip multiprocessor architecture. We use an FPGA-based rapid prototyping system to verify the functionality of our architecture in a network application scenario before fabricating the ASIC in a modern CMOS standard cell technology. The rapid prototyping environment gives us the opportunity to test our multiprocessor architecture with Ethernet-based data streams in a real network scenario. Our system concept is based on a massively parallel processor structure. Due to its regularity, our architecture can be easily scaled to accommodate a wide range of packet processing applications with various performance and throughput requirements at high reliability. Furthermore, the composition based on predefined building blocks guarantees fast design cycles and simplifies system verification. We present standard cell synthesis results as well as a performance analysis for a firewall application with various couplings of hardware accelerators. Finally, we compare implementations of our architecture with state-of-the-art desktop CPUs. We use simple, general-purpose applications as well as the introduced packet processing tasks to determine the performance capabilities and the resource efficiency of the GigaNetIC architecture. We show that, if supported by the application, parallelism offers more opportunities than increasing clock frequencies.

Validating Families of Latency Insensitive Protocols

With increasing clock frequencies, the signal delay on some interconnects in a System on Chip (SoC) often exceeds the clock period, which necessitates latency insensitive protocols (LIPs). The correctness of a system composed of synchronous blocks communicating via LIPs is established by showing latency equivalence between a completely synchronous composition of the blocks, and the LIP-based composition. Every time a new LIP is conceived, it needs to be debugged and then proven correct. Mathematical theorems to establish correctness, though elegant, are error prone, and tedious to create for every new variant of LIPs. In this work, we present validation frameworks for families of LIPs, both for dynamic validation, useful for early debug cycles, and formal verification for formal proof of correctness. This can be a useful framework in the hands of designers trying to create new LIPs or to optimize existing ones for design convergence.

Control speculation for energy-efficient next-generation superscalar processors

Conventional front-end designs attempt to maximize the number of in-flight instructions in the pipeline. However, branch mispredictions cause the processor to fetch useless instructions that are eventually squashed, increasing front-end energy and issue queue utilization and, thus, wasting around 30 percent of the power dissipated by a processor. Furthermore, processor design trends lead to increasing clock frequencies by lengthening the pipeline, which puts more pressure on the branch prediction engine since branches take longer to be resolved. As next-generation high-performance processors become deeply pipelined, the amount of wasted energy due to misspeculated instructions will go up. The aim of this work is to reduce the energy consumption of misspeculated instructions. We propose selective throttling, which triggers different power-aware techniques (fetch throttling, decode throttling, or disabling the selection logic) depending on the branch prediction confidence level. Results show that combining fetch-bandwidth reduction along with select-logic disabling provides the best performance in terms of overall energy reduction and energy-delay product improvement (14 percent and 10 percent, respectively, for a processor with a 22-stage pipeline and 16 percent and 13 percent, respectively, for a processor with a 42-stage pipeline).

Two-layer bus routing for high-speed printed circuit boards

The increasing clock frequencies in high-end industrial circuits bring new routing challenges that cannot be handled by traditional algorithms. An important design automation problem for high-speed boards today is routing nets within tight minimum and maximum length bounds. In this article, we propose an algorithm for routing bus structures between components on two layers such that all length constraints are satisfied. This algorithm handles length extension simultaneously during the actual routing process so that maximum resource utilization is achieved during length extension. Our approach here is to process one track at a time, and choose the best subset of nets to be routed on each track. The algorithm we propose for single-track routing is guaranteed to find the optimal subset of nets together with the optimal solution with length extension on one track. The experimental comparison with a recently proposed technique shows the effectiveness of this algorithm both in terms of solution quality and run-time.

A Functional Programming Framework for Latency Insensitive Protocol Validation

Latency insensitive protocols (LIPs) have been proposed as a viable means to connect synchronous IP blocks via long interconnects in a system-on-chip. The reason why one needs to implement LIPs on long interconnects stems from the fact that with increasing clock frequencies, the signal delay on some interconnects exceeds the clock period. Correctness of a system composed of synchronous blocks communicating via LIPs is established by showing latency equivalence between a completely synchronous composition of the blocks, and the LIP based composition. A design flow based on a synchronous composition specification, and stepwise refinement to LIP composition can be easily conceived, and a proof obligation to show latency equivalence between the synchronous specification and the refinement needs to be discharged. In this work, we propose a functional programming based framework for modeling and simulating LIP, and implement the semantics of various refinement steps in the programming model, so we can validate the LIP model against the original system within this functional programming framework. Such validation becomes easier due to the inherent denotational model of functional languages. We specifically use Standard ML to model the original system implementation as well as its latency insensitive version and compare the two by creating a model that contains both, giving them the same inputs and checking their outputs to be latency equivalent.

Effects of On-Chip Inductance on Power Distribution Grid

With increase of clock frequency, on-chip wire inductance starts to play an important role in power/ground distribution analysis, although it has not been considered so far. We perform a case study work that evaluates relation between decoupling capacitance position and noise suppression effect, and we reveal that placing decoupling capacitance close to current load is necessary for noise reduction. We experimentally show that impact of on-chip inductance becomes small when on-chip decoupling capacitance is well placed according to local power consumption. We also examine influences of grid pitch, wire area, and spacing between paired power and ground wires on power supply noise. When effect of on-chip inductance on power/ground noise is significant, minification of grid pitch is more efficient than increase in wire area, and small spacing reduces power noise as we expected.

Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines

One of the most important problems faced by microarchitecture designers is the poor scalability of some of the current solutions with increased clock frequencies and wider pipelines. As several studies show, internal processor structures scale differently with decreasing device sizes. While in some cases the access latency is determined by the speed of the logic circuitry, for others it is dominated by the interconnect delay. Furthermore, while some stages can be super-pipelined with relatively small performance loss, others must be kept atomic. This paper proposes a possible solution to this problem, avoiding the traditional trade-off between parallelism and clock speed. First, allowing instructions to enter and leave the Issue Window in an asynchronously manner enables faster speeds in the front-end at the expense of small synchronization latencies. Second, using an Execution Cache for storing instructions that are already scheduled allows for bypassing the issue circuitry and thus clocking the execution core at higher frequencies. Combined, these two mechanisms result in a 50% to 60% performance increase for our test microarchitecture, without requiring a completely new scheduling mechanism. Furthermore, the proposed microarchitecture requires significantly less energy, with 30% reduction in a 0.13um or 20% in a 0.06um process technology over the original baseline.

Experimental validation of crosstalk simulations for on-chip interconnects using S-parameters

Since the design of advanced microprocessors is based on simulation tools, accurate assessments of the amount of crosstalk noise are of paramount importance to avoid logic failures and less-than-optimal designs. With increasing clock frequencies, inductive effects become more important, and the validity of assumptions commonly used in simulation tools and approaches is unclear. We compared accurate experimental S-parameters with results derived from both magneto-quasi-static and full-wave simulation tools for simple crosstalk structures with various capacitive and inductive couplings, in the presence of parallel and orthogonal conductors. Our validation approach made possible the identification of the strengths and weaknesses of both tools as a function of frequency, which provides useful guidance to designers who have to balance the tradeoffs between accuracy and computation expenses for a large variety of cases

Exploiting temporal loads for low latency and high bandwidth memory

Increasing clock frequencies and issue rates aggravates the memory latency problem, imposing higher memory bandwidth requirements. While caches can be multi-ported to provide high memory bandwidth, the increase in access latency with the increase in the number of ports limits their potential. The paper proposes a novel technique, called the 'temporal load cache architecture', to reduce load latencies and provide higher memory bandwidths. The key motivation for the technique is that temporal loads - dynamic instances of a static load instruction that access the same address as that accessed by the last dynamic instance of the same static load - constitute 48% of all dynamic loads on average for the SPEC2000 benchmarks. When a load is predicted to be temporal, the data predicted to be accessed by it are read early in the pipeline from a small temporal load cache that stores the temporal data. The proposed temporal load cache architecture has two main advantages. First, since instructions dependent on a temporal load are provided with their data early in the pipeline, they can be issued as soon as they resolve their remaining data dependences and resource conflicts. Second, since a large percentage of loads can be filtered by the temporal load cache, the main data cache can service other (nontemporal) loads better, providing higher memory bandwidth. The experimental results show that the proposed temporal load cache architecture improves performance by 8.3% on average for the SPEC2000 integer benchmarks.

Reset noise in active pixel image sensors

In most image sensor pixel architectures, signal detection involves the reset of charge in a capacitive node. This operation gives rise to reset noise, and in particular, partition noise. In modern day transistors, with the shrinkage of device critical dimensions and increase of clock frequency, reset noise impacts many aspects of active pixel sensor operation. An additional spurious noise component has been observed from the reset noise model that is closely related to the switching operation, and is known as partition noise. Partition noise has been found to relate closely to the fall times of the applied reset pulse. However, existing noise models assume a constant charge density at the onset of transistor pinch-off, thus resulting in an underestimation of partition noise. This work investigates the influence of reset noise and other related noise generation on active pixel sensor performance.

Speeding up processing with approximation circuits

Current microprocessors employ a global timing reference to synchronize data transfer. A synchronous system must know the maximum time needed to compute a function, but a circuit usually finishes computation earlier than the worst-case delay. The system nevertheless waits for the maximum time bound to guarantee a correct result. As a first step in achieving variable pipeline delays based on data values, approximation circuits can increase clock frequency by reducing the number of cycles a function requires. Instead of implementing the complete logic function, a simplified circuit mimics it using rough calculations to predict results. The results are correct most of the time, and simulations show improvements in overall performance in spite of the overhead needed to recover from mistakes.

Algorithmic optimizations for software-only MPEG-2 encoding

Till recently dedicated hardware has been required to perform real-time MPEG-2 video encoding. However, with increase in clock frequency and the introduction of video-specific instruction sets, general-purpose processors and DSPs can now approximate the function and performance of single-function hardware. In this paper, a software-only MPEG-2(MP@ML) video encoder implementation aimed at real-time operation on embedded platforms and general-purpose processors is described. The main contribution of this work is a set of algorithmic optimizations that significantly reduces the computational complexity of the encoding process while slightly degrading the subjective video quality compared to encoders that are more exhaustive.

Electrical properties of low-inductance barium strontium titanate thin film decoupling capacitors

Very low inductance capacitors using barium strontium titanate (BST) based thin film have been developed for use in decoupling applications for GHz LSI operations. Increasing clock frequency and integration density of high performance logic LSI such as CPU requires very low power line impedance over wide frequency ranges up to GHz order. BST thin film capacitors are promising for GHz LSI applications due to excellent electrical properties of low inductance and high capacitance. Low temperature sputter deposited BST thin films show high capacitance and good leakage properties. The fabricated thin film chip capacitors of 150 μm bump pitch show low equivalent series inductance (ESL) of 17 pH and low ESR of 0.05 Ω. Impedance of the chip capacitor at 1 GHz is 100 times lower than conventional multilayered ceramic capacitors (MLC). These results indicate that developed capacitors are suitable for the decoupling applications to GHz LSI operation.

Thermal-ADI - a linear-time chip-level dynamic thermal-simulation algorithm based on alternating-direction-implicit (ADI) method

Due to the dramatic increase of clock frequency and integration density, power density and on-chip temperature in high-end very large scale integration (VLSI) circuits rise significantly. To ensure the timing correctness and the reliability of high-end VLSI design, efficient and accurate chip-level transient thermal simulations are of crucial importance. In this paper, we develop and present an efficient transient thermal-simulation algorithm based on the alternating-direction-implicit (ADI) method. Our algorithm, thermal-ADI, not only has a linear run time and memory requirement , but is also unconditionally stable, which ensures that time step is not limited by any stability requirement. Extensive experimental results show that our algorithm is not only orders of magnitude faster than the traditional thermal-simulation algorithms, but also highly accurate and efficient in memory usage.

Globally updated mesochronous design style

In large-scale and high-speed digital systems, global synchronization has frequently been used to protect clocked I/O from data failure due to metastability. Synchronous design styles are widely used, easy to grasp and to implement, and also well supported by logic synthesis tools. There are many drawbacks with global synchronization. Most important is the relationship between physical size and maximum clock frequency, which will approach its limit as clock frequency and system size increase simultaneously. The purpose of this proposed Globally Updated Mesochronous (GUM) design style is to overcome those drawbacks by identifying all global signal links in the system and adding synchronization circuits to these. System level simplicity, inherited from synchronous design and its tool support, is retained. In this paper, the GUM design style is described, analyzed, and demonstrated. Experimental results from a large-scale high-speed system using three 0.8-/spl mu/m BiCMOS chips are given. The GUM design style is scaleable and suitable for future system-on-chip applications both on and among chips.