Increasing Clock Frequency Research Articles

Using microchannels to cool microprocessors: a transmission-line-matrix study

As microprocessors components density and clock frequency increase, so do heat dissipation. The heat results from Joule effect due to leakage currents in the components area or active region. This region is only few microns thick and can quickly reach destructing temperatures if heat is not quickly removed. On this critical issue depends the system reliability. The active region is separated from the ventilated heat sink by a silicon substrate and a metal integrated heat spreader, both hundreds of microns thick. This interface region is the microprocessor's heat transfer plate where heat exchange is achieved by conduction. Because of the localized heat source, the thermal spreading resistance of the interface region can be high. A novel way of spreading heat in that region is the use of microchannel arrays where an appropriate thermal compound or a phase change liquid can be trapped to increase heat transfer by conduction or to create micro-heat-pipes. Traditional cooling methods, with conventional and well optimised heat sinks, can then be used with less burden.In this paper, the Transmission-Line-Matrix (TLM) technique is used to simulate the effect of microchannels on the temperature distribution in the active region. To minimize the interface heat resistance various microchannel and patterns are examined. In this part of the work, the microchannels are filled with the heat spreader material copper or aluminium. The results show an improved thermal transient behaviour and a reduced active region temperature in steady state.

End of Moore's law: thermal (noise) death of integration in micro and nano electronics

The exponential growth of memory size and clock frequency in computers has a great impact on everyday life. The growth is empirically described by Moore's law of miniaturization. Physical limitations of this growth would have a serious impact on technology and economy. A thermodynamical effect, the increasing thermal noise voltage (Johnson–Nyquist noise) on decreasing characteristic capacitances, together with the constrain of using lower supply voltages to keep power dissipation manageable on the contrary of increasing clock frequency, has the potential to break abruptly Moore's law within 6–8 years, or earlier.

Test Generation for Crosstalk-Induced Faults: Framework and Computational Results

Due to technology scaling and increasing clock frequency, problems due to noise effects lead to an increase in design/debugging efforts and a decrease in circuit performance. This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital combinational circuits. These noise effects can propagate through a circuit and create a logic error in a latch or at a primary output. We have developed a mixed-signal test generator, called XGEN, that incorporates classical static values as well as dynamic signals such as transitions and pulses, and timing information such as signal arrival times, rise/fall times, and gate delay. In this paper we first discuss the general framework of the test generation algorithm followed by computational results. Comparison of results with SPICE simulations confirms the accuracy of this approach.

Impact of three-dimensional architectures on interconnects in gigascale integration

An interconnect distribution model for homogeneous, three-dimensional (3-D) architectures with variable separation of strata is presented. Three-dimensional architectures offer an opportunity to reduce the length of the longest interconnects. The separation of strata has little impact on the length of interconnects but a large impact on the number of interstratal interconnects. Using a multilevel interconnect methodology for an ITRS 2005 100 nm ASIC, a two-strata architecture offers a 3.9/spl times/ increase in wire-limited clock frequency, an 84% decrease in wire-limited area or a 25% decrease in the number of metal levels required. In practice, however, such fabrication advances as improved alignment tolerances in wafer-bonding techniques are needed to gain key advantages stemming from 3-D architectures for homogeneous gigascale integrated circuits.

Self-tested self-synchronization circuit for mesochronous clocking

In large-scale and high-speed systems, global synchronization has been commonly used to protect clocked I/O from data read failure caused by metastability. There are many drawbacks with global synchronization, which will approach its physical limit in the future as system clock frequency and system scale increase simultaneously. Mesochronous clocking overcomes these drawbacks, but without a proper delay or phase control, a metastability problem occurs. Self-tested self-synchronization (STSS) was proposed to solve this problem. In this paper, we describe two STSS methods, STSS-1 and STSS-2, implemented by two-phase input ports for parallel/serial data transfer. Measurements on a test chip for the two methods show that a data rate of 750 Mb/s is reached with 3.6-V power supply in 0.6-/spl mu/m CMOS. Comparison is made between STSS-1 and STSS-3.

Emerging on-ship debugging techniques for real-time embedded systems

The increased clock frequencies and higher integration levels of today's high-performance embedded microcontrollers have led to the widespread incorporation of on-chip debugging logic into new microcontroller chip designs. The newly defined standard for embedded system debugging, the IEEE-ISTO Nexus 5001 Forum Standard for a Global Embedded Debug Interface, is introduced and is related to the test and debugging requirements of development engineers.

A multithreaded PowerPC processor for commercial servers

This paper describes the microarchitecture of the RS64 IV, a multithreaded PowerPC® processor, and its memory system. Because this processor is used only in IBM iSeries™ and pSeries™ commercial servers, it is optimized solely for commercial server workloads. Increasing miss rates because of trends in commercial server applications and increasing latency of cache misses because of rapidly increasing clock frequency are having a compounding effect on the portion of execution time that is wasted on cache misses. As a result, several optimizations are included in the processor design to address this problem. The most significant of these is the use of coarse-grained multithreading to enable the processor to perform useful instructions during cache misses. This provides a significant throughput increase while adding less than 5% to the chip area and having very little impact on cycle time. When compared with other performance-improvement techniques, multithreading yields an excell ent ratio of performance gain to implementation cost. Second, the miss rate of the L2 cache is reduced by making it four-way associative. Third, the latency of cache-to-cache movement of data is minimized. Fourth, the size of the L1 caches is relatively large. In addition to addressing cache misses, pipeline “holes” caused by branches are minimized with large instruction buffers, large L1 I-cache fetch bandwidth, and optimized resolution of the branch direction. In part, the branches are resolved quickly because of the short but efficient pipeline. To minimize pipeline holes due to data dependencies, the L1 D-cache access is optimized to yield a one-cycle load-to-use penalty.

A software-based real-time MPEG-2 video encoder

Dedicated hardware previously has been required to perform real-time MPEG-2 video encoding. However, with increases in clock frequency and the introduction of video-specific instruction sets, general-purpose processors can now approximate the function and performance of single-function hardware. In this paper, we describe a software-only MPEG-2 (MP@ML) video encoder implemented on a personal computer using an Intel/sup TM/ Pentium(R) III processor. This encoder is capable of real-time operation while consuming less than 70% of the processor. The main contribution of this work is a set of algorithmic simplifications that significantly reduces the computational load of the encoding process while only slightly degrading the subjective video quality compared to encoders that are more exhaustive.

Nuclear magnetic resonance quantum computing using liquid crystal solvents

Liquid crystals offer several advantages as solvents for molecules used for nuclear magnetic resonance quantum computing (NMRQC). The dipolar coupling between nuclear spins manifest in the NMR spectra of molecules oriented by a liquid crystal permits a significant increase in clock frequency, while short spin-lattice relaxation times permit fast recycling of algorithms, and save time in calibration and signal-enhancement experiments. Furthermore, the use of liquid crystal solvents offers scalability in the form of an expanded library of spin-bearing molecules suitable for NMRQC. These ideas are demonstrated with the successful execution of a two-qubit Grover search using a molecule (13C 1HCl3) oriented in a liquid crystal and a clock speed eight times greater than in an isotropic solvent. Perhaps more importantly, five times as many logic operations can be executed within the coherence time using the liquid crystal solvent.

Time characteristics of a Josephson-balanced comparator

We consider the time characteristics of a balanced comparator formed by two Josephson junctions connected in series. Such a decision-making junction pair is an essential component of all RSFQ cells. The analysis is performed within the framework of a simple time-dependent oscillator model. Turn-on delay and uncertainty (jitter) of comparator switching times are analysed taking into account the influence of thermal fluctuations and the finite time duration of clock pulse. Restrictions on speed performance of RSFQ cells caused by both times are considered. Some practical recommendations on the clock frequency increase are also discussed.

An analytical delay model

Delay consideration has been a major issue in design and test of high performance digital circuits. The assumption of input signal change occurring only when all internal nodes are stable restricts the increase of clock frequency. It is no longer true for wave pipelining circuits. However, previous logical delay models are based on the assumption. In addition, the stable time of a robust delay test generally depends on the longest sensitizable path delay. Thus, a new delay model is desirable. This paper explores the necessity first. Then, Boolean process to analytically describe the logical and timing behavior of a digital circuit is reviewed. The concept of sensitization is redefined precisely in this paper. Based on the new concept of sensitization, an analytical delay model is introduced. As a result, many untestable delay faults under the logical delay model can be tested if the output waveforms can be sampled at more time points. The longest sensitizable path length is computed for circuit design and delay test.

Conquering noise in deep-submicron digital ICs

As feature sizes decrease and clock frequencies increase, noise is becoming a greater concern in digital IC design. The authors describe a verification metric, noise stability, which guarantees functionality in the presence of noise, and a CAD technique, static noise analysis, for applying this metric on a chipwide basis.

Incorporating interconnect, register, and clock distribution delays into the retiming process

A retiming algorithm is presented which includes the effects of variable register, clock distribution, and interconnect delays. These delay components are incorporated into the retiming process by assigning register electrical characteristics (RECs) to each edge in the graph representation of a synchronous circuit. A matrix, called the sequential adjacency matrix (SAM), is presented that contains all path delays. Timing constraints for each data path are derived from this matrix. Vertex lags are assigned ranges rather than single values as in existing retiming algorithms. The approach used in the proposed algorithm is to initialize these ranges with unbounded values and to continuously tighten these ranges using localized timing constraints until an optimal solution is obtained. A branch and bound method is offered for the general retiming problem where the REC values are arbitrary. Certain monotonicity constraints can be placed on the REC values to permit the use of standard linear programming methods, thereby requiring significantly less computational time. These conditions and the feasibility of their application to practical circuits are presented. The algorithm is demonstrated on modified benchmark circuits and both increased clock frequencies and the elimination of all race conditions are observed.

Buffered Clock Tree Synthesis with Non-Zero Clock Skew Schedulingfor Increased Tolerance to Process Parameter Variations

An integrated top-down design system is presented in this paper for synthesizing clock distribution networks for application to synchronous digital systems. The timing behavior of a synchronous digital circuit is obtained from the register transfer level description of the circuit, and used to determine a non-zero clock skew schedule which reduces the clock period as compared to zero skew-based approaches. Concurrently, the permissible range of clock skew for each local data path is calculated to determine the maximum allowed variation of the scheduled clock skew such that no synchronization failures occur. The choice of clock skew values considers several design objectives, such as minimizing the effects of process parameter variations, imposing a zero clock skew constraint among the input and output registers, and constraining the permissible range of each local data path to a minimum value. The clock skew schedule and the worst case variation of the primary process parameters are used to determine the hierarchical topology of the clock distribution network, defining the number of levels and branches of the clock tree and the delay associated with each branch. The delay of each branch of the clock tree is physically implemented with distributed buffers targeted in CMOS technology using a circuit model that integrates short-channel devices with the signal waveform shape and the characteristics of the clock tree interconnect. A bottom-up approach for calculating the worst case variation of the clock skew due to process parameter variations is integrated with the top-down synthesis system. Thus, the local clock skews and a clock distribution network are obtained which are more tolerant to process parameter variations. This methodology and related algorithms have been demonstrated on several MCNC/ISCAS-89 benchmark circuits. Increases in system-wide clock frequency of up to 43% as compared with zero clock skew implementations are shown. Furthermore, examples of clock distribution networks that exploit intentional localized clock skew are presented which are tolerant to process parameter variations with worst case clock skew variations of up to 30%.

Low power microelectronics: retrospect and prospect

The era of low power microelectronics began with the invention of the transistor in the late 1940's and came of age with the invention of the integrated circuit in the late 1950's. Historically, the most demanding applications of low power microelectronics have been battery operated products such as wrist watches, hearing aids, implantable cardiac pacemakers, pocket calculators, pagers, cellular telephones and prospectively the hand-held multi-media terminal However, in the early 1990's low power microelectronics rapidly evolved from a substantial tributary to the mainstream of microelectronics. The principal reasons for this transformation were the increasing packing density of transistors and increasing clock frequencies of CMOS microchips pushing heat removal and power distribution to the forefront of the problems confronting the advance of microelectronics. The distinctive thesis of this discussion is that future opportunities for low power gigascale integration (GSI) will be governed by a hierarchy of theoretical and practical limits whose levels can be codified as: (1) fundamental, (2) material, (3) device, (4) circuit, and (5) system.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Copper-Based Metallization in ULSI Structures: Part II: Is Cu Ahead of Its Time as an On-Chip Interconnect Material?

The demand for manufacturing integrated circuit (IC) devices such as dynamic random access memory (DRAM), static random access memory (SRAM), electrically erasable and programmable read only memory (EEPROM) and logic devices with high circuit speed, high packing density and low power dissipation requires the downward scaling of feature sizes in ultralarge-scale integration (ULSI) structures. When chip size becomes smaller, the propagation delay time in a device is reduced. However, the importance of on-chip interconnect RC (resistance capacitance) delay to chip performance, reliability, and processing cost is increasing dramatically. When interconnect feature size decreases and clock frequencies increase, RC time delays become the major limitation in achieving high circuit speeds. The miniaturization of interconnect feature size also severely penalizes the overall performance of the interconnect, such as increasing interconnect resistance and interconnect current densities, which lead to reliability concerns due to electromigration. Lower resistance metal and lower dielectric materials are being considered to replace current Al and SiO2 interconnect materials. Innovative efforts in circuit design, process development, and the implementation of new materials can provide solutions. This issue of the MRS Bulletin focuses on the industrial viewpoint of copper interconnects. (A previous issue of the MRS Bulletin, June 1993, addressed university research approaches to copper metallization.) Articles in this issue, from six major semiconductor companies—IBM, Motorola, AT&amp;T Bell Laboratories, SEMATECH/National Semiconductor, NTT, and Fujitsu—provide a real-world viewpoint of the challenges faced when replacing aluminum with copper. The articles published in both issues also contain a comprehensive list of references (more than 300) to articles, patents, and device applications related to copper metallization for ULSI applications.

An architectural approach for increasing clock frequency and communication speed in monolithic WSI systems

Based on a special pipelining technique, a new methodology for increasing the clock frequency and communication speed in monolithic WSI systems is proposed. SPICE simulations show that the clock frequency on a synchronous wafer-scale system, implemented using a 1.2 /spl mu/m CMOS technology, can be operated well above 140 MHz, which is approximately five times the maximum frequency of current systems. It is also shown that frequencies higher than 1 GHz can be achieved if the technique is pushed to its limits. The methodology can be applied to interconnection networks as well, thereby improving their speed by approximately the same factor. In order to assess the various design tradeoffs imposed by the technique, a prototype communication interface has been designed using 1.2 /spl mu/m CMOS standard cells. This interface is intended to be used in a special distributed-queue, dual-bus (DQDB) communication network.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A bipolar population counter using wave pipelining to achieve 2.5* normal clock frequency

Wave pipelining is a technique for pipelining digital systems that can increase clock frequency in practical circuits without increasing the number of storage elements. In wave pipelining, multiple coherent waves of data are sent through a block of combinational logic by applying new inputs faster than the delay through the logic. The throughput of a 63-b CML (current mode logic) population counter was increased from 97 to 250 MHz using wave pipelining. The internal circuit is flow-through combinational logic. Novel CAD methods have balanced all input-to-output paths to about the same delay. This allows multiple data waves to propagate in sequence when the circuit is clocked faster than its propagation delay.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Supervisory signal transmission by modulating the mB1C code complementary bit

A supervisory signal transmission method for digital optical communication systems is proposed. It minimizes circuit scale, clock frequency increase, and interference between traffic and supervisory information, and does not require customization. The supervisory signal is carried by the amplitude-modulated complementary bit in the mB1C coded sequence. The code adds a single bit after every m bit block as a complement to the last bit of the block. Clock frequency increase is kept at a level of (m+1)/m. This additional bit is called the C bit. If the C bit's amplitude is modulated according to the supervisory (SV) signal and the main data block is not modulated, traffic and supervisory information can be isolated in time over the same fiber transmission. >

High-speed Viterbi decoder memory design

Two initial designs are presented to highlight some of the problems encountered in high-speed Viterbi memory design and to illustrate that a pointer-based path-history storage/retrieval system reduces the number of interconnections between memory cells and makes efficient use of path history memory. Unfortunately, this process suffers from the need for a large increase in clock frequency, which apparently limits its use in high-speed Viterbi decoders. Four principle designs are presented to show how the need for an increase in clock frequency may be overcome through the use of the data stream structure, code multiplexing, a form of double buffering and a pipelined trace-back architecture which is suitable for VLSI implementation.