High-speed Viterbi decoder memory design

Abstract

Two initial designs are presented to highlight some of the problems encountered in high-speed Viterbi memory design and to illustrate that a pointer-based path-history storage/retrieval system reduces the number of interconnections between memory cells and makes efficient use of path history memory. Unfortunately, this process suffers from the need for a large increase in clock frequency, which apparently limits its use in high-speed Viterbi decoders. Four principle designs are presented to show how the need for an increase in clock frequency may be overcome through the use of the data stream structure, code multiplexing, a form of double buffering and a pipelined trace-back architecture which is suitable for VLSI implementation.