Design of multi-gigabit DSP receivers

Abstract

Summary form only given, as follows. DSP equalizers and Viterbi decoders offer several advantages over analog techniques in backplane, serdes (serializer-deserializer), and optical transmission systems. However, the long critical paths in these DSP algorithms impose constraints on the achievable speed and limit the utility of these algorithms for high-speed applications, operating in the range of 3.125-10 Gbps. There are several techniques which exploit pipelining, parallel processing and retiming to design high-speed DFE receivers and Viterbi decoders. Some serdes systems also impose latency constraints. High-speed Viterbi decoders (such as 10 Gbps) with significantly less latency have been designed. The implementation of 10-gigabit fiber and copper systems may be approached in different ways.