Abstract
Convolutional codes are widely used in many communication systems due to their excellent error-control performance. High-speed Viterbi decoders for convolutional codes are of great interest in high-speed applications. A high-speed (2, 1, 6) Viterbi decoder is presented in this paper, which is based on parallel Radix-4 architecture and bit-level carry-save algorithm (CSA). In this design, the architecture of add-compare-select unit in Viterbi algorithm is improved, and the carry chain of traditional Ripple-Carry Adder is eliminated. Therefore, the critical path of Viterbi decoder is shortened: and the decoder achieved a high decoding throughput. The proposed Viterbi decoder has great chances to be applied to Ultra-Wide Band communication systems.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
