Increasing Clock Frequency Research Articles

Investigation of timing margin in single-flux-quantum 4 bit adders for increasing clock frequency of gate-level-pipelined circuits

This study investigates the timing margin required to handle fluctuations and variations in superconductor single-flux-quantum gate-level-pipelined adders; a smaller timing margin would improve the clock frequencies of gate-level-pipelined circuits. To evaluate timing margins, we demonstrated three 4 bit adders with 50-, 75-, and 100 GHz target clock frequencies using a 1.0 μm process. We estimated that the required timing margin of the adders was 2.1 ps. This indicates that previously reported gate-level-pipelined circuits operating at 30–60 GHz could operate at higher clock frequencies by reducing the timing margins.

Study of Existing Combination Circuits using CMOS and QCA Technology to Compare Their Efficacy

The potential limitations on the future advancement of microelectronics regular circuit scaling may arise from high power consumption and design intricacy. Therefore, it is imperative to introduce elective innovation to enhance future designs. The utilization of QCA for combinational circuit implementation represents a cutting-edge technological advancement that aims to address the scaling challenges faced by modern electronic devices. The circuit is characterized by the configuration of quantum cells in this logic design technique. This technique relies on the concept of computing through a field connection The utilization of QCA offers many benefits, such as reduced spatial requirements, elimination of interconnects, increased clock frequency, and the potential for low-power processing due to the absence of electron movement. This paper offers a comprehensive comparative analysis of various combinational circuits such as Full adder, MUX, XOR etc. that are considered essential in the field, by utilizing CMOS innovation and QCA nanotechnology.

Fast Response Prediction Method Based on Bidirectional Long Short-Term Memory for High-Speed Links

There is a recognized need to evaluate the performance of high-speed links accurately and quickly with increasing clock frequency. To evaluate the performance of the systems, the transient simulation method and the fast time-domain simulation method are adopted. Unfortunately, neither method can guarantee both the efficiency and accuracy of the results at the same time. In this article, a modeling method that can overcome the shortcomings of both the transient simulation method and the fast time-domain simulation method is proposed for obtaining responses of high-speed links based on bidirectional long short-term memory (Bi-LSTM). Here, the pulse response and response of a certain number of bits are first simulated or measured, which are used to determine training datasets. Then, the Bi-LSTM-based model uses the generated training datasets to build a precise model. Next, the developed model predicts the response of the high-speed link. Compared to the transient simulation method and fast time-domain simulation method, the results show that the proposed method can consider both accuracy and efficiency. In addition, 33 simulation experiments are performed to demonstrate the robustness of the proposed method. Finally, the accuracy of the proposed method is validated by comparing the measured and predicted results of the high-speed links with different nonlinearities.

High Performance FPGA Implementation of Single MAC Adaptive Filter for Independent Component Analysis

Blind source separation (BSS) is the process of extracting sources from mixed data without or with limited awareness of the sources. This paper uses field programmable gate array (FPGA) to create an effective version of the Blind source separation algorithm (ICA) with a single Multiply Accumulate (MAC) adaptive filter and to optimize it. Recently, space research has paid a lot of attention to this technique. We address this problem in two sections. The first approach is ICA, which seeks a linear revolution that can enhance the mutual independence of the mixture to distinguish the source signals from mixed signals. The second is a powerful flexible finite impulse response (FIR) filter construction that makes use of a MAC core and is adaptable. The adjustable coefficient filters have been used in the proposed study to determine the undiscovered system utilizing an optimal least mean square (LMS) technique. The filter tap under consideration in this paper includes 32 taps, and hardware description language (HDL) and FPGA devices were used to carry out the analysis and synthesis of it. When compared to the described architecture, the executed filter architecture uses 80% fewer resources and increases clock frequency by nearly five times, and speed is increased up to 32%.

Reconfigurable Architecture for Noise Cancellation in Acoustic Environment Using Single Multiply Accumulate Adaline Filter

The creation of multiple applications with a higher level of complexity has been made possible by the usage of artificial neural networks (ANNs). In this research, an efficient flexible finite impulse response (FIR) filter structure called ADALINE (adaptive linear element) that makes use of a MAC (multiply accumulate) core is proposed. The least mean square (LMS) and recursive least square (RLS) algorithms are the most often used methods for maximizing filter coefficients. Despite outperforming the LMS, the RLS approach has not been favored for real-time applications due to its higher design arithmetic complexity. To achieve less computation, the fundamental filter has utilized an LMS-based tapping delay line filter, which is practically a workable option for an adaptive filtering algorithm. To discover the undiscovered system, the adjustable coefficient filters have been developed in the suggested work utilizing an optimal LMS approach. The 10-tap filter being considered here has been analyzed and synthesized utilizing field programmable gate array (FPGA) devices and programming in hardware description language. In terms of how well the resources were used, the placement and postrouting design performed well. If the implemented filter architecture is compared with the existing filter architecture, it reveals a 25% decrease in resources from the existing one and an increase in clock frequency of roughly 20%.

A Novel Multiplier Hardware Organization for Finite Fields Defined by All-One Polynomials

In this brief, a novel, energy-efficient hardware organization for a finite-field multiplier based on irreducible all-one polynomials (AOPs) is proposed. The proposed AOP multiplier organization deploys three distinct submodules, which constitute a left-shifting network (reduction), an AND network (multiplication), and a three-input XOR tree (accumulation). Previously reported state-of-the-art implementation distributes these operations to systolic arrays, which are elegant in layout but do not yield the most efficient solution. The advantages of the proposed organization compared with those reported in the literature include reduced cost and power dissipation for a given clock frequency constraint (or increased clock frequency for a given power constraint) and the absence of bypassing problems due to fewer pipeline stages. Both the previously reported and the proposed organizations have been implemented in Verilog for three different binary-field sizes using the TSMC 90 nm standard cell library and have been synthesized for three distinct frequency targets using Cadence Genus Synthesis tool. The proposed organization achieves 18%, 31%, and 19% reduction in average leakage, dynamic capacitance, and area, respectively, compared with state-of-the-art schemes and thus can be considered for energy-efficient, compact portable systems, including wireless sensors.

TokenSmart: Distributed, Scalable Power Management in the Many-core Era

Centralized power management control systems are hitting a scalability limit. In particular, enforcing a power cap in a many-core system in a performance-friendly manner is quite challenging. Today’s on-chip controller reduces the clock speed of compute domains in response to local or global power limit alerts. However, this is opaque to the operating system (OS), which continues to request higher clock frequency based on the workload characteristics acting against the centralized on-chip controller. To address these issues, we introduce TokenSmart, which implements a set of scalable distributed frequency control heuristics within the OS, using a novel token-based mechanism. The number of system-allocated power tokens represents the maximum allowable power consumption; and the OS governor orchestrates a token-passing (or sharing) algorithm between the compute engines. Token allocation count increase (decrease) corresponds to a increase (decrease) of clock frequency. The compute units are connected in a ring-topology allowing minimal meta-data to be passed along with the token value for regulating power budget. We explore different heuristics to assign tokens smartly across the units. This results in efficient power regulation and sustenance of turbo frequencies over a longer duration. Our proposed methodology can be implemented in hardware with multiple on-chip controllers, or in software where each set of cores acts as a compute unit. The methodology is currently implemented within the Linux kernel of a real IBM POWER9 many-core system and experimentally verified on different real world workloads such as Redis, Cassandra, PostgreSQL along with a micro-benchmark such as rt-app. Our experiments indicate the increase in throughput for all the workloads along with the benefit of power savings. For instance, results show a considerable boost of about 4% in throughput of both the PostgreSQL and Redis benchmark with a substantial savings in power consumption (18% and 37%, respectively). If the approach is implemented in hardware, then our experimental analysis speculates the throughput to increase up to 14% in PostgreSQL benchmark.

Analysis on the Method of Enhanced Transient State of DLDO

As an important unit of power management system, traditional analog low-dropout regulator (ALDO) is widely used in System-on-Chip (SoC) design to provide stable and pure power for each sub-circuit block. However, in ultra-low-power design applications, low quiescent current greatly affects the loop gain of ALDO. Digital low-dropout regulator (DLDO) has good low-voltage working ability, process scalability and diversified control schemes, which is more suitable for low-power SoC design. However, a large number of digital circuits with fast switching devices will produce large load current changes, so DLDO needs fast transient response speed to adjust load changes. In recent years, DLDO can be divided into synchronous DLDO and asynchronous DLDO according to different control methods. Among them, the design structure of synchronous DLDO is relatively simple. It depends on an independent global clock, and there is a tradeoff between speed, accuracy and power consumption. When the clock frequency increases, the system needs fast transient response, but the power consumption will increase proportionally, and the current efficiency and loop stability will decrease. Using large output capacitor to deal with load transient is not conducive to improve chip integration. Although asynchronous DLDO can improve the response speed based on the advantages of asynchronous control scheme, the stability of DLDO will face greater risks. Therefore, this paper will introduce several transient response enhancement technologies that do not sacrifice system power consumption, accuracy or stability. It includes adaptive frequency technology and fast response algorithm to improve the transient response speed of synchronous DLDO, event-driven solution and coarse and fine adjustment technology to improve the transient response speed of asynchronous DLDO. On this basis, a typical DLDO structure with excellent performance in the recent 10 years is given.

Accurate Small Signal Simulation of Superconductor Interconnects in SPICE

Superconductor electronics is gaining traction as the increasing density of integration of recent and future digital circuits pushes the limits of available simulation models. Designers often make assumptions in the behavioral models of circuit elements when simulating circuits. For instance high-frequency effects have been neglected so far in the design of superconductor digital circuits, while much has been done in the past to model them. Indeed these effects had little influence on the accuracy of digital circuits simulations until recently. The increase in clock frequency, combined with longer paths between cells and higher yield requirements for large scale circuits fabrication, has led to the need of more accurate models, including in particular high frequency effects such as quasi-particle losses. To do so, this work uses a state-space model that describes the circuit under study with internal state variables and a set of first-order differential equations. We extract the state-space model while analytically enforcing the DC requirements of superconductors that are required to account for flux-trapping. The model accurately traps flux at DC, and given the model is fitted with enough poles, the high-frequency effects are also accurate relative to the reference model. The high-frequency effects have been investigated on a practical circuit: a long-distance Passive Transmission Line (PTL) designed for the high-density MIT Lincoln Labs SFQ5ee process. Results obtained in the time domain allow to observe the effects of dispersion of pulses traveling on long paths of PTLs. Indeed the energy of voltage pulses is sufficient to break Cooper pairs for the highest clock frequencies.

A stealthy Hardware Trojan based on a Statistical Fault Attack

Integrated Circuits (ICs) are sensible to a wide range of (passive, active, invasive, non-invasive) physical attacks. In this context, Hardware Trojans (HTs), that are malicious modifications of a circuit by an untrusted manufacturer, are one of the most challenging threats to mitigate. HTs aim to alter the functionality of the infected chip in a malicious way, e.g. under specific conditions known by the adversary. Fault attacks are a typical attack vector. However, for a HT to be exploitable by an adversary, it also has to be stealthy. For example, a HT that would directly inject exploitable faults in a block cipher may be spotted by analyzing its functional behavior (i.e. the positions and the distribution of the faulty values appearing). In this paper, we propose a stealthy HT instance leading to successful and hidden Statistical Fault Attacks (SFA). More precisely, the faults are injected when the chip is running under condition for which metastabilty occurs (i.e. with a increased clock frequency), leading to the apparition faults at random positions within the target implementation. In addition, an internal bit is set to a value known only by the adversary, allowing him to perform efficient SFA. Compared to classical SFA, the HT uses its control on the target to circumvent behavioral detection tests. Indeed, it also adds computation errors in the early rounds of the target cipher which are not exploitable via SFA.

Performance and security of 5 GHz repetition rate polarization-based quantum key distribution

We present and characterize a source for a 5 GHz clocked polarization-based simplified BB84 protocol. Secret keys are distributed over 151.5 km of standard telecom fiber at a rate of 54.5 kbps. Potentially, an increased clock frequency of the experiment introduces correlations between succeeding pulses. We discuss the impact of these correlations and propose measurements to estimate the relevant parameters.

A 1.45 GHz All-Digital Spread Spectrum Clock Generator in 65nm CMOS for Synchronization-Free SoC Applications

The increase of clock frequency in digital circuits exacerbates the electromagnetic interference (EMI) between devices. Spread-spectrum techniques reduce the electromagnetic noise lowering harmonic peaks of the clock signal by means of frequency modulation. In System-on-Chips (SoCs) another requirement in many applications is the coexistence of both modulated and un-modulated clock domains. In these cases, suitable synchronization systems are used to allow data to cross the boundary between spread and un-spread clock domains. In this paper we present a spread-spectrum clock generator (SSCG) able to provide both spreaded and un-spreaded clocks. The spreaded clock has a specially designed modulation profile, allowing at the same time a seamless synchronization-free interface between spreaded and un-spreaded clock domains and a large EMI reduction. The paper presents the derivation of the new highly discontinuous modulation profile (that allows to achieve an EMI reduction up to 15.8dB) and implementation details of an all-digital SSCG able to provide the developed modulation waveform. A test chip has been fabricated in UMC 65nm CMOS technology, using a novel dual-output digitally controlled delay line. The circuit can generate both spread and un-spread clocks (double output mode) or the spread clock alone (single output mode). Area occupation is 0.102mm2, whereas power consumption is 48.5mW in double output mode and 34mW in single output mode.

A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus Routing

As clock frequencies increase, topology-matching bus routing is desired to provide an initial routing result which facilitates the following buffer insertion to meet the timing constraints. In this article, we present a complete topology-matching bus routing framework considering nonuniform track configurations. In the framework, a bus clustering technique is proposed to reduce the routing complexity by grouping buses sharing similar pin locations. To perform topology-matching routing in a nonuniform track configuration, we propose a directed acyclic graph-based algorithm to connect a bus in a specific topology. Furthermore, a rip-up and reroute scheme is applied to alleviate the routing congestion. Compared with the state-of-the-art topology-matching bus routers, our proposed algorithm significantly improves the routing quality and reduces the number of spacing violations in comparable runtime.

Energy-Efficient Thermal-Aware Scheduling for RT Tasks Using TCPN

This work leverages TCPNs to design an energy-efficient, thermal-aware real-time scheduler for a multiprocessor system that normally runs in a low state energy at maximum system utilization but its capable of increasing the clock frequency to serve aperiodic tasks, optimizing energy, and honoring temporal and thermal constraints. An off-line stage computes the minimum frequency required to run the periodic tasks at maximum CPU utilization, the proportion of each task’s job to be run on each CPU, the maximum clock frequency that keeps temperature under a limit, and the available cycles (slack) with respect to the system with minimum frequency. Then, a Zero-Laxity online scheduler dispatches the periodic tasks according to the offline calculation. Upon the arrival of aperiodic tasks, it increases clock frequency in such a way that all periodic and aperiodic tasks are properly executed. Thermal and temporal requirements are always guaranteed, and energy consumption is minimized.

A Static Analysis for the Minimization of Voters in Fault-Tolerant Circuits

We present a formal approach to minimize the number of voters in triple-modular redundant (TMR) sequential circuits. Our technique actually works on a single copy of the TMR circuit and considers a large class of fault mo dels of the form “at most 1 Single-Event Upset (SEU) or Single-Event Transient (SET) every k clock cycles”. Verification-based voter minimization guarantees that the resulting TMR circuit (i) is fault tolerant to the soft-errors defined by the fault model and (ii) is functionally equivalent to the initial TMR circuit. Our approach operates at the logic level and takes into account the input and output interface specifications of the circuit. Its implementation makes use of graph traversal algorithms, fixed-point iterations, and binary decision diagrams (BDD). Experimental results on the ITC’99 benchmark suite indicate that our method significantly decreases the number of inserted voters, yielding a hardware reduction of up to 55% and a clock frequency increase of up to 35% compared to full TMR. As our experiments show, if the SEU fault-model is replaced with the stricter fault-model of SET, it has a minor impact on the number of removed voters. On the other hand, BDD-based modelling of SET effects represents a more complex task than the modelling of an SEU as a bit-flip. We propose solutions for this task and explain the nature of encountered problems. We address scalability issues arising from formal verification with approximations and assess their efficiency and precision.

A Fault-Tolerant Cache System of Automotive Vision Processor Complying With ISO26262

With fluctuating voltage, widening operating temperature, and increasing clock frequency, cache systems are becoming increasingly susceptible to transient errors. Error correction code (ECC) is an attractive approach for transient error detection and correction. However, redundant memory for ECC has a significant impact on cost and increases the transient error rates. This brief presents a fault-tolerant cache system of automotive vision processors. The cache system has the small redundant memory and decreases the transient error rates with the proposed mechanism, which increases the error recovery rate and is considered with data cache characteristics. Also, the cache system is analyzed complying with ISO26262. As a result, thanks to 80% reduction of error traps caused by the cache system at the automotive vision processor’s variable fault-tolerant policy, compared to the cache system of the state-of-art vision processors for automotive.

(Invited) Monolithic Integration of n-In0.53Ga0.47As and p-Ge FinFETs on Si

With continuous increase in transistor count and clock frequency, the power density of current Si integrated circuits has reached a level that calls for a revolutionary change in transistor technology. High hole mobility Ge and high electron mobility InGaAs have been considered to be the most promising channel materials for p-channel and n-channel MOSFETs, respectively. Selective-area growth (SAG) on nano-trenches has been quite popular in integrating III-V materials with Si substrates. Since there exists a high lattice mismatch between III-V materials and Si, obtaining defect-free epilayer is still a great challenge. In this work, we demonstrate selective area growth of InGaAs on Ge trenches aiming at integrating n-channel InGaAs FinFETs and p-channel Ge FinFETs side by side on a Si substrate for CMOS applications. The Ge templates, which were grown on Si by chemical vapor deposition, were prepared by etching through an oxide mask using a dilute H2O2 solution to create Ge linear trench structures with embedded {111} facets at the bottom of the trenches for facilitating the regrowth of III-V materials. The III-V materials were selectively grown on the patterned Ge templates by metal-organic vapor phase epitaxy. An InGaP buffer layer, which has a wide bandgap and is beneficial for electrical isolation between the channel and substrate, was grown onto the Ge trenches. Undoped InGaAs was grown on InGaP as the n-channel material. High resolution transmission microscopy investigations show that very few dislocations are present near the Ge/InGaP interface in the trenches. It is found that In content of InGaP increases from 50 % to about 70 % with growth as evidenced by energy-dispersive x-ray spectroscopy (EDX). Interestingly, composition grading is also observed on the subsequently grown InGaAs. It begins from an In0.21Ga0.79As layer, which has good lattice match to the In0.7Ga0.3P layer beneath, then changes to the nominal In0.71Ga0.29As layer near the top of the fin. The strain in InGaAs is partially released through the generation of dislocations near the InGaAs/InGaP interface, leading to a nearly defect-free region at the top of the fin. A growth mechanism is proposed to account for the correlation between strain accommodation, composition grading, and defects generation.

DeMixGen: Deterministic Mixed-Signal Layout Generation With Separated Analog and Digital Signal Paths

With shrinking process technology, decreasing supply voltage, and increasing clock frequency, noise reduction becomes more and more crucial to the success of modern mixed-signal system-on-chip design. To eliminate the switching noise due to crosstalk coupling between analog and digital signals, it is essential to fully separate the routing paths of analog and digital nets when generating mixed-signal layouts. Different from previous works which cannot fully separate analog and digital routing paths, this paper presents a novel hierarchical deterministic mixed-signal layout synthesis approach with the separation of analog and digital signal paths for switching noise elimination. Experimental results based on a third-order $ {\Sigma \Delta }$ modulator show that the proposed approach can result in various layouts with separated analog and digital signal paths while achieving better signal-to-noise and distortion ratio, and overall performance specifications.

Avoiding the Brain Damage

The pursuit of low losses and low distortion are necessary conditions to improve the signal integrity. As mentioned in [1], it is sometimes said that thereare two types of engineers—those who have signal integrityproblems and those who will.As clock frequencies increase,magnifying signal integrityproblems, this saying willbecome even more accurate.On the other hand, the usage of the technology is now a day unavoidable. Thus, to avoid the electromagnetic radiationdirectly on the brain, should be recomendablethe useof the hand off device since the integrated inalambric amplifiers of new generation genertea lot of energy (power). Besides, it is convenient that the user of that technology be aware to the activities he is doing to avoid accidents mainly when he is manipulating some kind of equipment or driving a vehicle.As mentioned in[2], the power amplifier (PA) is a critical component whitin a WLAN transmitter because PA performance affects wireless coverage area, data rate capacity, and battery life.Â

Optimizing performance-per-watt on GPUs in high performance computing

The magnitude of the real-time digital signal processing challenge attached to large radio astronomical antenna arrays motivates use of high performance computing (HPC) systems. The need for high power efficiency (performance per watt) at remote observatory sites parallels that in HPC broadly, where efficiency is an emerging critical metric. We investigate how the performance per watt of graphics processing units (GPUs) is affected by temperature, core clock frequency and voltage. Our results highlight how the underlying physical processes that govern transistor operation affect power efficiency. In particular, we show experimentally that GPU power consumption grows non-linearly with both temperature and supply voltage, as predicted by physical transistor models. We show lowering GPU supply voltage and increasing clock frequency while maintaining a low die temperature increases the power efficiency of an NVIDIA K20 GPU by up to 37-48% over default settings when running xGPU, a compute-bound code used in radio astronomy. We discuss how temperature-aware power models could be used to reduce power consumption for future HPC installations. Automatic temperature-aware and application-dependent voltage and frequency scaling (T-DVFS and A-DVFS) may provide a mechanism to achieve better power efficiency for a wider range of codes running on GPUs