(Invited) Monolithic Integration of n-In0.53Ga0.47As and p-Ge FinFETs on Si

Abstract

With continuous increase in transistor count and clock frequency, the power density of current Si integrated circuits has reached a level that calls for a revolutionary change in transistor technology. High hole mobility Ge and high electron mobility InGaAs have been considered to be the most promising channel materials for p-channel and n-channel MOSFETs, respectively. Selective-area growth (SAG) on nano-trenches has been quite popular in integrating III-V materials with Si substrates. Since there exists a high lattice mismatch between III-V materials and Si, obtaining defect-free epilayer is still a great challenge. In this work, we demonstrate selective area growth of InGaAs on Ge trenches aiming at integrating n-channel InGaAs FinFETs and p-channel Ge FinFETs side by side on a Si substrate for CMOS applications. The Ge templates, which were grown on Si by chemical vapor deposition, were prepared by etching through an oxide mask using a dilute H2O2 solution to create Ge linear trench structures with embedded {111} facets at the bottom of the trenches for facilitating the regrowth of III-V materials. The III-V materials were selectively grown on the patterned Ge templates by metal-organic vapor phase epitaxy. An InGaP buffer layer, which has a wide bandgap and is beneficial for electrical isolation between the channel and substrate, was grown onto the Ge trenches. Undoped InGaAs was grown on InGaP as the n-channel material. High resolution transmission microscopy investigations show that very few dislocations are present near the Ge/InGaP interface in the trenches. It is found that In content of InGaP increases from 50 % to about 70 % with growth as evidenced by energy-dispersive x-ray spectroscopy (EDX). Interestingly, composition grading is also observed on the subsequently grown InGaAs. It begins from an In0.21Ga0.79As layer, which has good lattice match to the In0.7Ga0.3P layer beneath, then changes to the nominal In0.71Ga0.29As layer near the top of the fin. The strain in InGaAs is partially released through the generation of dislocations near the InGaAs/InGaP interface, leading to a nearly defect-free region at the top of the fin. A growth mechanism is proposed to account for the correlation between strain accommodation, composition grading, and defects generation.