Increase Of Gate Oxide Thickness Research Articles

Total ionizing dose hardness analysis of transistors in commercial 180 nm CMOS technology

The very large scale integrated (VLSI) circuits become susceptible to soft errors mainly due to exposure to harsh environmental conditions. In this paper, the analysis of total ionizing dose (TID) effects on single gate NMOS, enclosed gate NMOS (ELT NMOS), and single gate PMOS are carried out for 180 nm CMOS technology. The various MOS architectures were exposed to radiation using Cobalt-60 (Co60) radiation source. The charge density distribution at pre-radiation and post-radiation condition for all the three above said structures are observed. It is observed that the threshold voltage shift for the single gate NMOS device is about 25 times more in comparison to the ELT NMOS device after radiation at 30 Å (Å) gate oxide thickness. The transfer characteristics (drain current versus gate to source voltage) of single gate NMOS is compared for TID from 0 krad to 500 krad with a step size of 100 krad at different oxide thicknesses from 15 Å to 75 Å. It is observed that the drain current increases with an increase in total dose in the sub-threshold region for lower gate oxide thickness (15 Å to 45 Å) while with the increase of gate oxide thickness (beyond 60 Å), the drain current increases significantly for the higher gate to source voltage also. The drain saturation current decreases with the increase of oxide thickness from 15 Å to 75 Å. The impact of TID on single gate PMOS is analysed and no significant effect of radiation observed on threshold voltage or leakage current. The leakage current shift is the least for single gate PMOS among the single gate NMOS, ELT NMOS, and single gate PMOS after radiation of 500 krad total dose. The layouts are designed in Cadence virtuoso software and simulated in Visual TCAD software.

Effect of Gate Oxide Thickness on Negative Bias Temperature Instability in p-Mosfet with Sion Gate Dielectrics

The major reliability issue of metal-oxide-semiconductor field-effect-transistor (MOSFET) had been mainly hot carrier injection (HCI) until the late 1990s. However, negative bias temperature instability (NBTI) has been focused on since late 1990s until now because both aggressive scaling-down of gate oxide thickness and nitrogen incorporation into gate oxide, which mitigate HCI, enhance NBTI severely [1-2]. Although the phenomenon of bias temperature instability (BTI) has been known for several decades, there is still no clear explanation regarding the roles of gate oxide thickness on NBTI degradation of p-MOSFETs. For example, N. Kimizuka et al. reported that NBTI lifetime in p-MOSFET with thin gate oxide is larger than that with thick gate oxide under equivalent oxide field stress in the range of 2.0 ~ 4.0 nm oxide thickness [3]. On the contrary, S. Mahapatra et al. reported that BTI could be enhanced in p-MOSFET with thinner gate oxide due to high diffusivity of H2 in gate poly [4]. Meanwhile, G. Pobegen et al. reported that NBTI were all the same in p-MOSFETs with gate oxide thickness of 5.6, 13.9 and 29.1 nm [5]. In this work, we tried to resolve conflicting experimental results reported in the literature: Since the reduction of gate oxide thickness will enhance electric field across gate oxide, the application of thinner gate oxide will deteriorate NBTI degradation such like threshold voltage shift (ΔVt) caused by charge generation. However, it also increases oxide capacitance, reducing the effect of generated positive charge which is one of the main sources for NBTI degradation. We fabricated p-MOSFET devices with SiON gate oxide and p+ poly-silicon gate stack in the commercial graded production line through conventional DRAM full processes. We evaluated p-MOSFETs with two different thicknesses of gate oxide: One is p-MOSFETs with thin gate oxide of 3.36 nm (‘thin PMOS’ hereafter), and the other is p-MOSFETs with gate oxide of 7.27 nm (‘thick PMOS’ hereafter). We evaluated NBTI degradation electrically by measuring the threshold voltage (Vt) before and after NBT stress for 1,000 seconds at 125 °C with Agilent 4156C. By means of stressing for 1,000 seconds without a break and by measuring just after stress, we could minimize undesirable variations caused by recovery. Data shown in Fig. 1(a) represent ΔVt caused by NBT stress of various gate voltages. In Fig. 1(a), the slope of ΔVt for thin PMOS devices is steeper than that of thick PMOS. However, if we redraw the same data of ΔVt as a function of oxide electric field (Eox), then we have the same ΔVtslope for both thin and thick PMOS devices regardless of gate oxide thickness, as shown in Fig. 1(b). NBTI has been known to be exponentially increased with oxide electric field [6], which expressed empirically as Eq. (1). Our NBTI data of both thin and thick PMOS have the identical B value of 0.69 cm/MV. Also, NBTI is generally known to be caused by both interface trap and positive oxide charge which were generated during the NBT stress [6]. The generated charges contribute to threshold voltage shift via Eq. (2). Therefore, the total increased charge density (ΔNtotal) can be written as Eq. (3). By using Eq. (3), the correlation between the increased trap density and the oxide field applied during the NBT stress test can be obtained from the data in Fig. 1(b), and the result is shown in Fig. 1(c), in which all data lay on the one straight line. This suggests that NBT stress with the equivalent oxide field causes the same amount of increased charges independent of gate oxide thickness. Therefore, Eq. (1) must be normalized by Coxto count this observation as Eq. (4). As shown in Fig. 2, it is remarkable that NBTI degradation becomes the minimum at the condition of Eq. (5). NBTI drops drastically down to the minimum point and then rises with the increase of gate oxide thickness, which accounts for the previous conflicting experimental results. In summary, we found that the total increased charge density of the devices subjected to NBT stress is same as long as the equivalent electric field is applied, regardless of gate oxide thickness. By modifying the empirical equation for ΔVt, we suggest that the optimal value of Tox can be selected for a given gate voltage and oxide field acceleration coefficient. This finding can be served as the new guideline on selecting gate voltage and gate oxide thickness to minimize the NBTI degradation both for process development and integrated circuit design. Figure 1

Comparison of Random-Dopant-Induced Threshold Voltage Fluctuation in Nanoscale Single-, Double-, and Surrounding-Gate Field-Effect Transistors

In this study, we explore random-dopant-induced threshold voltage fluctuation by solving a quantum correction model. Fluctuation of the threshold voltage for three nanoscale transistors, single-, double-, and surrounding-gate (SG, DG, and AG) metal–oxide–semiconductor field-effect transistors (MOSFETs) are computationally compared. To calculate the variance of the threshold voltages of the SG, DG, and AG MOSFETs, a quantum correction model under equilibrium conditions is expanded and numerically solved using perturbation and monotone iterative methods. Fluctuation of the threshold voltage resulting from the random dopant, gate oxide thickness, channel film thickness, gate channel length, and device width are calculated for the three devices. Quantum mechanical and classical results give similar predictions for fluctuation of the threshold voltage with respect to different parameters including the dimensions of the device and the channel doping. Fluctuation increases when the channel doping concentration, channel film thickness, and gate oxide thickness increase. On the other hand, it decreases when the channel length and device width increase. Calculation results of the quantum correction model are quantitatively higher than those of classical estimation in accordance with different quantum confinement effects in nanoscale SG, DG, and AG MOSFETs. It is found that the AG MOSFET has the smallest threshold voltage fluctuation among the three device structures due to its good channel controllability. In contrast to the conventional quantum Monte Carlo approach and the small-signal analysis of the Schrödinger–Poisson equations, this computationally cost-effective quantum correction approach shows acceptable accuracy and is ready for industrial technology computer-aided design application.

A study of threshold voltage fluctuations of nanoscale double gate metal-oxide-semiconductor field effect transistors using quantum correction simulation

In this paper, we computationally investigate fluctuations of the threshold voltage introduced by random dopants in nanoscale double gate metal-oxide-semiconductor field effect transistors (DG MOSFETs). To calculate variance of the threshold voltage of nanoscale DG MOSFETs, a quantum correction model is numerically solved with the perturbation and the monotone iterative techniques. Fluctuations of the threshold voltage resulting from the random dopant, the gate oxide thickness, the channel film thickness, the gate channel length, and the device width are calculated. Quantum mechanical and classical results have similar prediction on fluctuations of the threshold voltage with respect to different designing parameters including dimension of device geometry as well as the channel doping. Fluctuation increases when the channel doping, the channel film thickness, and/or the gate oxide thickness increase. On the other hand, it decreases when the channel length and/or the device width increase. Calculations of the quantum correction model are quantitatively higher than that of the classical estimation according to different quantum confinement effects in nanoscale DG MOSFETs. Due to good channel controllability, DG MOSFETs possess relatively lower fluctuation, compared with the fluctuation of single gate MOSFETs (less than a half of the fluctuation[-11pc] of SG MOSFETs). To reduce fluctuations of the threshold voltage, epitaxial layers on both sides of channel with different epitaxial doping are introduced. For a certain thickness of epitaxial layers, the fluctuation of the threshold voltage decreases when epitaxial doping decreases. In contrast to conventional quantum Monte Carlo approach and small signal analysis of the Schrodinger-Poisson equations, this computationally efficient approach shows acceptable accuracy and is ready for industrial technology computer-aided design application.

An approach for quantum mechanical modeling and simulation for MOS devices, covering the whole operation region

A quantum mechanical (QM) approach for modeling and simulation of MOS devices, covering the whole operation region, was proposed. This formulation is applicable continuously from the subthreshold to the saturation regions, since it exactly treats the QM effects on the in-depth distribution of the gate induced carriers in the channel by solving one dimensional Poisson equation and Schrödinger equation self-consistently and it treats the lateral drift–diffusion transport using quasi-Fermi potential. A QM simulator was implemented using this QM approach. This QM simulator was verified by classical three-dimensional device simulator, CADDETH, in the whole range of operation of bulk MOSFET with low dopant density where QM effect is negligible. The QM simulation elucidated that the threshold voltage shift in thin SOI MOSFETs in saturation region as well as in linear region results from energy shift of the lowest conduction electron level and effective increase of gate oxide thickness.

Design considerations for 25 nm MOSFET devices

This paper presents the results of a systematic theoretical investigation on scaling gate oxide thickness and the source-drain extension (SDE) junction depth to design high performance MOSFET devices with effective channel lengths near 25 nm. In order to obtain 25 nm MOSFETs, CMOS technologies with 40, 50, and 60 nm gate lengths were designed by scaling SDE junction depth to 14, 20, and 26 nm, respectively. Each technology with the target gate oxide thickness was optimized for an off-state leakage current ∼10 nA/μm for 25 nm devices and the device characteristics were obtained for an equivalent gate oxide thickness of 1, 1.5, and 2 nm. The results show that for a target off-state leakage current of 25 nm devices the magnitude of threshold voltage, sub-threshold slope, and drain-induced barrier lowering increases while the magnitude of drive current decreases with the increase of gate oxide thickness. On the other hand, the variation in the magnitude of threshold voltage, sub-threshold slope, drain-induced barrier lowering, and the drive current for the similar devices is insignificant within the range of SDE junction depth 14–26 nm. It is, also, found that the gate delay for 25 nm devices increases with the increase of SDE junction depth. This study, clearly, demonstrates the importance of scaling gate oxide thickness and the SDE junction depth below the presently reported limits to design high performance 25 nm MOSFET devices for low voltage application.

Reverse short and narrow channel effects in n and p transistors: quantification of the enhanced diffusion and the gate oxide thickness increase

The threshold voltage (VT) of CMOS 6 IBM technology n and p transistors function of their length L was investigated. A reverse short channel effect (RSCE) was observed simultaneously on the n inverted and p buried channel transistors, i.e. a VT n( L) increase and a correlated VT p( L) decrease when L was decreased. The same effect was observed for narrower channels. After correction of the standard short channel effect, the correlation between VT n( L) and VT p( L) was explained by two components: first a boron oxidation enhanced diffusion in the channel during the sidewall polysilicon gate oxidation; second, an increase of the gate oxide electrical thickness inversely proportional to the gate conductor width. This thickness increase was interpreted as due to a contaminant diffusion from the gate stack sidewall during the sidewall oxidation, either oxygen producing a physical thickness increase, or fluorine reducing the oxide dielectric constant.

Slight gate oxide thickness increase in PMOS devices with BF2 implanted polysilicon gate

The gate oxide thickness increase in PMOSFET devices with BF/sub 2/ implanted p/sup +/ polysilicon gate is observed even when rapid thermal annealing (RTA) is used as a dopant activation thermal process. The increase of oxide thickness is studied as a function of RTA temperature, RTA time, and initial oxide thickness in the 35 /spl Aring/ regime and is being reported for the first time. It was found that oxide thickness increase could be as significant as 7% in this regime. This phenomenon can be explained by the model of fluorine incorporation, which is found to he effectively suppressed with nitrogen implanted in the polysilicon.

P-channel metal–oxide–semiconductor dosimeter fading dependencies on gate bias and oxide thickness

The threshold voltage recovery (‘‘fading’’) of P-channel metal–oxide–semiconductor dosimeters irradiated to 10 Gy(Si), after 3500 h room-temperature annealing, has been investigated. The obtained results have shown that fading decreases with the increase of the absolute value of gate voltage as well as with the increase of gate oxide thickness.

Direct evidence of gate oxide thickness increase in tungsten polycide processes

The increase of the effective gate oxide thickness for W-polycide processes is studied. The samples with as-deposited and annealed W polycide were analyzed by secondary ion mass spectrometry, transmission electron microscopy (TEM), and high-frequency CV measurements. The TEM cross section shows that the gate oxide thicknesses are approximately 244 and approximately 285 AA for as-deposited and 1000 degrees C annealed samples, respectively. The TEM results agree with those from CV measurements. The TEM analyses provide direct physical evidence of an additional oxide thickness ( approximately 41 AA) during the W-polycide annealing.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>